ak4631 ETC-unknow, ak4631 Datasheet
ak4631
Available stocks
Related parts for ak4631
ak4631 Summary of contents
Page 1
... Mono CODEC with ALC & MIC/SPK-AMP AK4631はマイクアンプ、スピーカアンプを内蔵した16bit モノラルCODECです。入力にはマイクアン ...
Page 2
... PMADC ALC1 (IPGA) ADC HPF ALC1A PMDAC DACA DAC DVOL BEEPA ALC1M DACM PMSPK ALC2 PMBP BEEP MIN MOUT Figure 1. AK4631 Block Diagram - 2 - [AK4631] AVSS AVDD PDN Audio FCK Interface BICK SDTO SDTI CSN Control CCLK Register CDTI PMPLL MCKO PLL ...
Page 3
... AK4631VN AKD4631 AK4631評価用ボード ピン配置 VCOM AVSS AVDD VCOC PDN CSN CCLK MS0317-J-01 28pin QFN (0.5mm pitch Top View MIN 20 SVSS 19 SVDD 18 SPN SPP 17 16 MCKO 15 MCKI [AK4631] 2004/11 ...
Page 4
... AK4536, AK4630 を使用している場合、下記で示す互換性の中で塗りつぶされた箇所以外は、回路およびソ フトの変更無しで AK4536 または AK4630 をAK4631 へ置き換えることが可能です。 ...
Page 5
... Note 1 ...
Page 6
... Don’t care 3 1 Don’t care 6 1 Don’t care 7 Others Others 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz では AK4536/AK4630 と AK4631 の設定は同じです。 MS0317-J- PMVCM PMBP PMSPK BEEPS ...
Page 7
... Microphone Input Pin (Mono Input) MIC Power Supply Pin for Microphone - 7 - Function 設定 オープンかつパスを切って下さい。 オープン DVSSに接続 オープン [AK4631] 2004/11 ...
Page 8
... Note 3. AVSSと DVSS, SVSSは同じアナロググランドに接続して下さい。 Note 4. 実装されるプリント基板の配線密度100%以上の場合です。この電力値はAK4631の内部損失分で、外 ...
Page 9
... ADC, MIC Gain=20dB, IPGA=0dB, ALC1=OFF 0.168 =10kΩ SPP/SPN pins, ALC2=OFF, R =8Ω, BTL, SVDD=3.3V L 2.47 3. SPP/SPN pins, ALC2=OFF, C =3µ 6. [AK4631] typ max Units 30 40 kΩ 2.47 2. kΩ kΩ 0.5 0 +27 ...
Page 10
... EXTモード(PMPLL=MCKO=M/S= “0”)の場合、AVDD+DVDD = 7mA (fs=8kHz, typ)、9.5mA (fs=48kHz, typ)になります。 MS0317-J-01 min typ - 1.98 0.74 1.48 0.3 0 1. [AK4631] max Units - Vpp 2.22 Vpp 0.9 Vpp - Vpp 36 kΩ 2.18 Vpp - kΩ 17 µA 200 2004/11 ...
Page 11
... VIL (Iout=−80µA) VOH DVDD−0.4 (Iout= 80µA) VOL Iin - 11 - typ max 3.0 3.5 - 3.6 - 4.0 - ±0.1 17.1 0 0.62 - 1.81 - 3.99 - 3.6 3.6 - 4.0 - ±0.01 16.8 ±1.0 min typ max - - - - 30%DVDD - - - - 0.4 ± [AK4631] Units kHz kHz kHz kHz kHz dB dB 1/fs µ kHz kHz kHz dB dB 1/fs dB Units µA 2004/11 ...
Page 12
... S tFSD -70 tBSD -70 tSDH 50 tSDS [AK4631] typ max 27.0 256 x fFCK 1/16fFCK 1/32fFCK 1/64fFCK 50 0.5 x tBCK 0.5 x tBCK + 40 0.5 x tBCK 0.5 x tBCK + 2004/11 Units MHz ns ns ...
Page 13
... S mode) tFSD tBSD tSDH 50 tSDS [AK4631] typ max Units 8 26 1/fFCK-tBFCK 55 1/16fFCK 8 48 1/fFCK-tBFCK 55 1/16fFCK 1/32fFCK 1/64fFCK 27.0 MHz 256 x fFCK 1/fFCK-tBFCK 55 1/16fFCK 80 80 ...
Page 14
... PMADC “↑” to SDTO valid Note 27. AK4631はPDN pin = “L”でリセットされます。 Note 28. PMADC bitを立ち上げてからのFCKクロックの“↑”の回数です。 ...
Page 15
... Figure 3. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = “0”) MS0317-J-01 1/fCLK tCLKH tCLKL 1/fFCK dFCK dFCK 1/fMCK tMCKOH tMCKOL dMCK = tMCKOL x fMCK x 100 Figure 2. Clock Timing (PLL Master mode) tBCK tDBF tBSD MSB tSDS MSB - 15 - VIH VIL 50%DVDD 50%DVDD 50%DVDD dBCK 50%DVDD 50%DVDD 50%DVDD tSDH VIH VIL [AK4631] 2004/11 ...
Page 16
... FCK tBFCK BICK SDTO SDTI Figure 5. Audio Interface Timing (PLL Master mode & Except DSP mode) MS0317-J-01 tBCK tDBF dBCK tBSD tSDS tFSD tSDS tSDH - 16 - [AK4631] 50%DVDD 50%DVDD 50%DVDD 50%DVDD MSB tSDH VIH MSB VIL 50%DVDD dBCK 50%DVDD tBSD 50%DVDD VIH ...
Page 17
... Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1) MS0317-J-01 1/fFCK tFCKH tBCK tBCKH tBCKL 1/fFCK tFCKH tBCK tBCKH tBCKL - 17 - [AK4631] VIH VIL tBFCK VIH VIL VIH VIL VIH VIL tBFCK VIH VIL VIH ...
Page 18
... Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) MS0317-J-01 1/fCLK tCLKH tCLKL 1/fFCK tFCKH tFCKL tBCK tBCKH tBCKL 1/fMCK tMCKOH tMCKOL - 18 - [AK4631] VIH VIL VIH VIL VIH VIL 50%DVDD 2004/11 ...
Page 19
... Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) MS0317-J-01 tFCKH tFCKB tBSD MSB tSDS MSB tFCKH tFCKB tBSD tSDS - 19 - VIH VIL VIH VIL VIH VIL 50%DVDD tSDH VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD MSB tSDH VIH MSB VIL [AK4631] 2004/11 ...
Page 20
... Figure 12. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode) MS0317-J-01 1/fCLK tCLKH tCLKL 1/fFCK tFCKH tFCKL tBCK tBCKH tBCKL Figure 11. Clock Timing (EXT Slave mode) tFCKB tFSD tBSD MSB tSDS tSDH - 20 - [AK4631] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL 2004/11 ...
Page 21
... Figure 14. WRITE Data Input Timing tPDV Figure 15. Power Down & Reset Timing 1 tPD Figure 16. Power Down & Reset Timing VIH VIL tCCKH VIH VIL tCCK tCDH VIH R/W VIL tCSW VIH VIL tCSH VIH VIL VIH VIL VIH VIL 50%DVDD VIL [AK4631] 2004/11 ...
Page 22
... MCKI pin BICK pin Master Clock 16fs/32fs/64fs Input for PLL Output (Note 30) Master Clock 16fs/32fs/64fs Input for PLL Input (Note 30) 16fs/32fs/64fs GND Input 256fs/ ≥ 32fs 512fs/ 1024fs Input Input [AK4631] - FCK pin 1fs Output 1fs Input 1fs Input 1fs Input 2004/11 ...
Page 23
... AK4631はパワーダウン時 (PDN pin = “L”)、及びリセット解除後はスレーブモードです。リセット解除後、 ...
Page 24
... N/A BICK pin FCK pin 不定 不定 “L” Output “L” Output 1fs Output See Table 9 MCKO bit = “1” 不定 不定 256fs Output [AK4631] 2004/11 ...
Page 25
... BICK 1fs FCK SDTO SDTI Figure 18. PLL Master Mode BCKO0 BCKO1 BICK出力周波数 Table 9. BICK Output Frequency at Master Mode - 25 - DSP or µP MCLK BCLK FCK SDTI SDTO 16fs Default 32fs 64fs N/A [AK4631] 2004/11 ...
Page 26
... PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) MCKI, BICK or FCK pinへ入力されるクロックを基準に内部のPLLにてAK4631に必要なクロックを生成しま ...
Page 27
... MCKI 32fs, 64fs BICK 1fs FCK SDTO SDTI Figure 21. EXT Slave Mode - 27 - Sampling Frequency Range 7.35kHz ≤ fs ≤ 48kHz Default 7.35kHz < fs ≤ 13kHz 7.35kHz < fs ≤ 48kHz 7.35kHz < fs ≤ 26kHz DSP or µP MCLK BCLK FCK SDTI SDTO [AK4631] 2004/11 ...
Page 28
... Table 12. Audio Interface Format BCKP bit Audio Interface Format 0 0 Figure Figure Figure Figure 25 Table 13. Audio Interface Format in Mode BICK Figure ≥ 16fs See Table 11 ≥ 32fs Figure 26 ≥ 32fs Figure 27 Default ≥ 32fs Figure 28 [AK4631] 2004/11 ...
Page 29
... Don’t Care 1/ Don’t Care 1/fs [AK4631 2004/11 ...
Page 30
... Don’t Care 1/ Don’t Care 1/fs [AK4631 2004/11 ...
Page 31
... Figure 27. Mode 2 Timing - Don’t Care Don’t Care Don’t Care Don’t Care [AK4631 2004/11 ...
Page 32
... AK4631はマイク用ゲインアンプを内蔵しています。MGAIN1-0 bits により、ゲインを設定することができま ...
Page 33
... AK4631はALC1 bit = “0”の時、マニュアルモードになります。このモードは以下の場合に使用します。 ...
Page 34
... Enable 1 Enable Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS ALC2 bit = “1” (default) (1) Addr=06H, Data=00H (2) Addr=08H, Data=47H (3) Addr=09H, Data=10H (4) Addr=07H, Data=61H [AK4631] 0dB 2004/11 ...
Page 35
... Figure 31. Block Diagram of BEEP pin BEEP SPP/SPN ゲイン +7.89dB +9.93dB +14.11dB +16.15dB Table 18 20kΩ 時、BEEP入力ゲイン Default fs=22.05kHz時 48msec 12msec BEEP AOUT ゲイン 0dB 0dB 0dB 0dB [AK4631] の i 2004/11 ...
Page 36
... PMAO bit = “1” かつ AOPSN bit = “0” でパワーアップ状態となります。 Figure 32. AOUT 外付け回路(ポップ音低減対策時) AOUTコントロールシーケンス(AK4631 のポップ音低減対策時 ...
Page 37
... Table 20 SPK-Amp 出力レベル [AK4631] ALC2 ON 時 SPK-Amp出力 3.09Vpp, 150mW@8Ω 3.92Vpp, 240mW@8Ω 使用不可 使用不可 使用不可 使用不可 6.34Vpp 8.02Vpp ...
Page 38
... MOUT pin – MIN pin 間のコンデンサと MIN pin の入力抵抗(Rin)によって構成される HPF の カットオフ周波数(fc)は以下のようになります。 66Hz@Rin=24kΩ(typ), 133Hz@Rin=12kΩ(min), 44Hz@Rin=36kΩ(max) MS0317-J-01 ≥10Ω SPP SPN ≥10Ω ZD Hi-Z >t1(Note [AK4631] ZD Hi-Z SVDD/2 Hi-Z >0 2004/11 ...
Page 39
... ALC2リミッタ動作 –7.1dBV 2/fs = 250µs 2/fs = 125µs あり (Timeout=512/fs) なし 0.5dB step SPKG1-0 bits ゲイン 00 +4.4dB 01 +6.4dB 10 +10.6dB 11 +12.7dB - 39 - [AK4631] ALC2リカバリ動作 –9.1dBV 512/fs = 64ms 512/fs = 32ms 1dB step 2004/11 ...
Page 40
... FS-6.0dB = -9.1dBV +6.0dB -15.1dBV +14.0dB -23.1dBV ALC2 SPK-AMP Figure 37. Speaker-Amp Output Level Diagram - 40 - 0.8dBV 0dBV -1.2dBV Full-differential +7.9dB Single-ended -5.2dBV +1.9dB -10dBV -20dBV -30dBV 10dBV Full-differential 2.8dBV 0.8dBV 0dBV +9.9dB Single-ended -3.2dBV +3.9dB -10dBV -20dBV -30dBV [AK4631] 2004/11 ...
Page 41
... FS-4dB = -7.1dBV -4.0dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV +6.0dB -15.1dBV +14.0dB -23.1dBV ALC2 SPK-AMP Figure 39. Speaker-Amp Output Level Diagram - 41 - 10dBV 7.0dBV Full-differential 5.0dBV Single-ended 1.0dBV 0dBV +8.1dB -10dBV -20dBV -30dBV 10dBV 9.1dBV Full-differential 7.1dBV Single-ended 3.1dBV 0dBV +10.2dB -10dBV -20dBV -30dBV [AK4631] 2004/11 ...
Page 42
... “0” “1” Chip Address (C1 = “1” “0”); Fixed to “10” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 40. Serial Control I/F Timing - [AK4631] 2004/11 ...
Page 43
... BEEPA ALC1M BCKO1 BCKO0 DIF1 BCKP FS2 WTM1 WTM0 LTM1 LMAT1 LMAT0 RATT REF3 REF2 REF1 IPGA3 IPGA2 IPGA1 DVOL3 DVOL2 DVOL1 RFS3 RFS2 RFS1 [AK4631 PMADC PMPLL MGAIN0 ALC1A DIF0 FS1 FS0 LTM0 LMTH REF0 IPGA0 DVOL0 RFS0 2004/11 ...
Page 44
... DAC, ALC1, ALC2のどれか一つでも使 用する場合はクロックを供給して下さい。 MS0317-J- PMVCM PMBP PMSPK PMAO PMDAC PMMIC [AK4631] D0 PMADC 0 2004/11 ...
Page 45
... MCKPD: MCKI pinのプルダウン抵抗コントロール 0: Master Clock input enable 1: Pull down by 25kΩ(typ.) (Default) M/S: Master / Slave Modeの選択 0: Slave Mode (Default) 1: Master Mode MS0317-J- M/S MCKPD MCKO [AK4631] D0 PMPLL 0 2004/11 ...
Page 46
... PMSPK bit =“0”となっているため、スピーカアンプはパワーダウン状態です。 MS0317-J- SPPS BEEPS ALC2S DACA MGAIN0 bit Input Gain 0 0 0dB 0 1 +20dB 1 0 +26dB 1 1 +32dB Table 23. Input Gain - DACM MPWR MICAD Default [AK4631] D0 MGAIN0 1 2004/11 ...
Page 47
... AOPSN SPKG1 MGAIN1 SPKG1-0 bits ゲイン 00 0dB 01 +2.2dB 10 +4.4dB 11 +8.7dB Table 24. SPK-Amp ゲイン ALC1M MIX DACM BEEPS ALC1A DACA BEEPA - SPKG0 BEEPA ALC1M ALC2S ALC2 SPK AOUT [AK4631] D0 ALC1A 0 2004/11 ...
Page 48
... BCKO1 BCKO0 DIF1 BICK Figure ≥ 16fs See Table 31 ≥ 32fs Figure 26 ≥ 32fs Figure 27 Default ≥ 32fs Figure 28 16fs Default 32fs 64fs N/A Input Frequency 1fs Default 16fs 32fs 64fs 11.2896MHz 12.288MHz 12MHz 24MHz 13.5MHz 27MHz [AK4631] D0 DIF0 0 2004/11 ...
Page 49
... N/A Sampling Frequency Range 7.35kHz ≤ fs ≤ 48kHz 7.35kHz < fs ≤ 13kHz 7.35kHz < fs ≤ 48kHz 7.35kHz < fs ≤ 26kHz Default [AK4631] D0 FS0 0 Default 2004/11 ...
Page 50
... Table 34. Zero Crossing Timeout Period - WTM1 WTM0 LTM1 16kHz Default 31µs 63µs 125µs 250µs 16kHz 8ms Default 16ms 32ms 64ms 16kHz 8ms Default 16ms 32ms 64ms [AK4631] D0 LTM0 0 2004/11 ...
Page 51
... ADC Input ≥ −6.0dBFS RATT GAIN STEP Table 36. ALC1 Recovery Gain Step Setting LMAT1 LMAT0 ATT STEP Table 37. ALC1 Limiter ATT Step Setting - LMAT1 LMAT0 RATT Default Default 1 Default [AK4631] D0 LMTH 0 2004/11 ...
Page 52
... DATA (HEX) Table 38. Setting Reference Value at ALC1 Recovery Operation MS0317-J- REF6 REF5 GAIN (dB) 47 +27.5 46 +27.0 45 +26 +19 +0 −5.0 06 −5.5 05 −6.0 04 −6.5 03 −7.0 02 −7.5 01 −8 REF4 REF3 REF2 REF1 STEP Default 0.5dB [AK4631] D0 REF0 0 2004/11 ...
Page 53
... DVOL7-0: 出力ディジタルボリューム(see Table 40) AK4631はMUTEを含む0.5dBステップ、 256レベルのディジタル出力ボリューム(DVOL)を内蔵しま ...
Page 54
... RFS6-0: ALC2リカバリ動作時の基準値の設定(see Table 41) REFS5-0 bits Table 41. Setting Reference Value at ALC2 Recovery Operation MS0317-J- RFS5 Volume[dB] Step 3F +19.5 3E +19.0 3D +18.5 3C +18 0.5dB 19 +0.5 18 +0 -10.5 02 -11.0 01 -11.5 00 -12 RFS4 RFS3 RFS2 RFS1 Default [AK4631] D0 RFS0 0 2004/11 ...
Page 55
... AK4631のAVSS, DVSS, SVSS と周辺コントローラ等のグランドは分けて配線して下さい。 - プルダウンピン以外のディジタル入力ピンはオープンにしないで下さい。 ...
Page 56
... AVDD (typ)を中心に出力され、スピーカ出力では SVDD/2を中心に出力されます。 MS0317-J- [AK4631] 2004/11 ...
Page 57
... PLL3-0, FS2-0, BCKO1-0, MSBS, BCKP, M/S bitの設定を行って下さい。 ...
Page 58
... FS2-0, PLL3-0, MSBS, BCKP bitの設定を行って下さい。 ...
Page 59
... PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP, M/S bitの設定を行って下さい。 ...
Page 60
... FS1-0 bitの設定を行って下さい。 ...
Page 61
... ALC1 Disable ALC1 Enable (6) (7) 1059 / fs Initialize Normal State Power Down Figure 47. MIC Input Recording Sequence - 61 - [AK4631] Example: PLL Master Mode Audio I/F Format:DSP Mode, BCKP=MSBS=“0” Sampling Frequency:8kHz Pre MIC AMP:+20dB MIC Power On ALC1 setting:Refer to Figrure 29 ALC2 bit=“1”(default) ...
Page 62
... Figure 48. Speaker-Amp Output Sequence - 62 - Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= “0” Sampling Frequency: 8kHz Digital Volume: -8dB ALC2 : Enable (1) Addr:05H, Data:00H (2) Addr:02H, Data:28H (3) Addr:07H, Data:40H (4) Addr:0AH, Data:28H (9) (5) Addr:00H, Data:54H (6) Addr:02H, Data:A8H Playback (7) Addr:02H, Data:28H Hi-Z (8) Addr:00H, Data:40H [AK4631] 2004/11 ...
Page 63
... SPK-AmpのパスのDisable: BEEPS bit = “1” → “0” (7) BEEP MS0317-J-01 Clocks can be stopped. 0 (2) 0 (3) (4) (5) Normal Output Hi-Z SVDD/2 Normal Output SVDD/2 Speaker-Amp” Output Sequence - 63 - Example: (1) Addr:07H, Data:00H (2) Addr:00H, Data:70H (6) (3) Addr:02H, Data:60H (4) Addr:02H, Data:E0H (7) BEEP Signal Output (5) Addr:02H, Data:60H (6) Addr:00H, Data:40H Hi-Z (7) Addr:02H, Data:00H [AK4631] 2004/11 ...
Page 64
... DACA bit: “1” → “0” MS0317-J-01 XXXX (6) XXXXXXX (5) Hi-Z Normal Output Figure 50. Mono Lineout Sequence - 64 - [AK4631] Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= “0” Sampling Frequency: 8kHz Digital Volume: -8dB (1) Addr:05H, Data:00H (2) Addr:02H, Data:10H (3) Addr:0AH, Data:28H (4) Addr:00H, Data:4CH ...
Page 65
... ASAHI KASEI 2. AK4631 内蔵のポップ音低減回路使用時 FS3-0 bits XXXX (Addr:05H, D5, D2-0) (1) DACA bit (2) (Addr:02H, D4) (3) DVOL7-0 bits 00011000 (Addr:0AH, D7-0) AOPSN bit (Addr:03H, D6) (4) PMDAC bit (Addr:00H, D2) PMAO bit (Addr:00H, D3) AOUT pin < ...
Page 66
... Input Master Clock Select at PLL Mode : 11.2896MHz Sampling Frequency:8kHz (1) (2) (3) Addr:01H, Data:0CH Stop an external MCKI Example Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) Addr:01H, Data:04H (2) Stop the external clocks [AK4631] 2004/11 ...
Page 67
... Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz (1) Addr:01H, Data:04H (2) Stop the external clocks Example Audio I/F Format :MSB justified(ADC and DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) Addr:01H, Data:04H (2) Stop the external clocks [AK4631] 2004/11 ...
Page 68
... Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0317-J-01 パッケージ 5.2 ± 0.20 5.0 ± 0.10 0.50 0.05 M 0.05 Epoxy Cu Solder plate (Pb free 0.60 ± 0.10 [AK4631] 2004/11 ...
Page 69
... Speaker-Amp電源に Note 6 を追加 “Note 6. 8 Ω ダイナミックスピーカ接続時はSVDD = 2.6V ∼ 3.6V です。 重要な注意事項 [AK4631] 2004/11 ...