ak7780 AKM Semiconductor, Inc., ak7780 Datasheet

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ak7780

Manufacturer Part Number
ak7780
Description
24bit 5ch Adc & Src + Audio Dsp
Manufacturer
AKM Semiconductor, Inc.
Datasheet
The AK7780 is a highly integrated audio processor, including a 28-bit floating point DSP, two 24-bit stereo
ADC’s and one mono ADC. The stereo ADC’s feature high performance, achieving 96dB dynamic range,
they include 8:1 input selectors. The ADC supports sampling frequencies from 7.35 kHz to 96 kHz. The
AK7780 also includes a stereo sample rate converter (SRC), so it can be used as a master device when
it receives digital audio inputs. The DSP includes 168kbits of SRAM for audio delay data that is suitable
for creating simulated surround fields. The programmable DSP block is realized with 2560step/fs DSP. It
supports sampling frequencies from 7.35kHz to 96 kHz. The AK7780 is used to implement complete
sound field control, such as echo, 3D, parametric equalization, and other sound enhancements. It is
packaged in a 100-lead LQFP package.
[DSP]
[ADC]
MS0581-E-00-PB
Main
4 channels (2 stereo pairs)
Word length: 28-bit (Data RAM F24.4 limited range floating point)
(SDOUT1,SDOUT2 and SDOUT3)
Instruction cycle time: 8.1 ns (2560step/fs fs=48kHz; 1280step/fs fs=96kHz)
Multiplier: 24 x 16 → 40-bit (Double precision available)
Divider: 24 / 24 → 24-bit
ALU: 44-bit arithmetic operation (overflow margin: 4-bits)
Shift+Register: Flexible setting
Program RAM: 2048 x 36-bit
Coefficient RAM: 2048 x 16-bit
Data RAM: 2048 x 28-bit (F24.4[sign bit + 23-bit mantissa + 4-bit exponent])
Offset RAM: 64 x 13-bit
Internal Delay RAM: 168kbits
Sampling frequency: 7.35kHz ~ 96kHz
Serial interface port for microcontroller or I
Master Clock: 2560fs (generated by PLL from 32fs ,64fs, 256fs and 384fs)
Master/Slave operation
Serial signal input port (10ch): MSB justified 24-bit / LSB justified 16/20/24-bit and I
Serial signal output port(12ch): MSB justified 24-bit / LSB justified 24,16-bit and I
S/(N+D): 92dB (fs = 48kHz)
Digital HPF (fc = 1Hz)
24-bit 64X over-sampling delta-sigma (fs = 7.35kHz ~ 96kHz)
DR, S/N: 96dBA (fs = 48kHz, fully-differential input)
/ 4096 x 28 bit + 4096 x 14 bit) 4 pattern setting
( 6144 x 28 bit / 2048 x 28 bit + 8192 x 14 bit / 3072 x 28 bit + 6144 x 14 bit
F24.4 arithmetic and logic operation
28bit = F24.4 [24 bit sign & mantissa: 4 bit exponent]
14bit = F10.4 [10 bit sign & mantissa: 4 bit exponent]
GENERAL DESCRIPTION
FEATURES
24bit 5ch ADC & SRC + Audio DSP
- 1 -
2
C BUS control
AK7780
2007/09
[AK7780]
2
S
2
S

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ak7780 Summary of contents

Page 1

... The ADC supports sampling frequencies from 7.35 kHz to 96 kHz. The AK7780 also includes a stereo sample rate converter (SRC can be used as a master device when it receives digital audio inputs. The DSP includes 168kbits of SRAM for audio delay data that is suitable for creating simulated surround fields ...

Page 2

... DR, S/N: 95dBA ( fs = 48kHz) Includes digital attenuator [SRC] Stereo pair Input frequency 7.35kHz ~ 96kHz → Output frequency 44.1kHz ~ 96kHz [Other] Power supply: +3.3V ±0.3V, +1.7V~+2.0V(typ +1.8V) Operating temperature range: -40°C~85°C Package: 100pin LQFP(0.5mm pitch) MS0581-E-00- [AK7780] 2007/09 ...

Page 3

... P_DSPRST S_RESET_N R_DSPRST_N P_ADRST R_ADRST_N ADRST_N INIT_RESET * Figure 1 shows a simplified diagram of the AK7780, which isn’t the perfect same as the actual circuit diagram. Each describes the relationship of reset control and target reset blocks. MS0581-E-00-PB BLOCK DIAGRAM ADCM ADC2 VOL MUX SELOA1[1:0] ...

Page 4

... Peak Detector Figure 2. DSP Block Diagram - 4 - DLP0,DLP1 DLRAM OFRAM 64w×13bit Micon I/F Control Serial I/F PRAM 2048w × 36bit PC Stack : 5level(max 8bi t SDIN6 SDIN5 SDIN4 SDIN3 SDIN2 SDIN1 SDOUT6 SDOUT5 SDOUT4 SDOUT3 SDOUT2 SDOUT1 [AK7780] 2007/09 ...

Page 5

... AINR+ 91 AINL- AINL AINR5 AINL5 94 AINR6 95 96 AINL6 97 AINR7 98 AINL7 99 AINR8 100 AINL8 MS0581-E-00-PB -40 ∼ +85°C 100pin LQFP(0.5mm pitch) Evaluation Board for AK7780 (TOP VIEW [AK7780 DVDD 48 DVSS 47 DVDD18 46 SCLK/SCL CAD0 RQ / CAD1 44 43 P_DSPRST 42 P_ADRST 41 P_CKRST 40 INIT_RESET ...

Page 6

... No Pin Name I/O Filter connection pin for AK7780 core PLL 1 LFLT O When using the PLL function, connect with R (1.5kΩ) and C (47nF) in series and connected to analog ground (AVSS) see. 9. System design (1) - Analog ground 0V 2 AVSS Power supply pin for analog section 3.3V (typ) 3 AVDD ...

Page 7

... DSP serial data input pin 35 SDIN5 I Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / not used, connect to DVSS MS0581-E-00-PB Function [AK7780] Classification System Clock Digital section 2 S. Serial output data Clock output Digital Power ...

Page 8

... DVDD Serial data output pin for microcomputer interfaces When RQ = “H” Hi-Z MS0581-E-00-PB Function 2 C Bus address setting pin Bus address pin bus data clock pin - 8 - [AK7780] Classification System Clock Digital power supply Reset Microcomputer Interface Microcomputer Interface ...

Page 9

... Analog ground 0V 74 AVSS RC Filter connection pin for SRC. 75 SRC_LFLT O See p.86 10-2-5-2: SRC PLL loop filter setting. MS0581-E-00-PB Function [AK7780] Classification Microcomputer Interface. Status Digital section Serial output data Clock output Digital power supply Conditional input Digital section Serial input data SRC 2 ...

Page 10

... Normal Microcontroller Interface bus compatible MS0581-E-00-PB Function I2CSEL INIT_RESET [AK7780] Classification TEST Analog input Analog Power Supply Analog input Analog output Analog input Analog Power Supply Analog input SDA L L “Hi-Z” → pull-up function 2007/09 ...

Page 11

... AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0581-E-00-PB ABSOLUTE MAXIMUM RATINGS Symbol min VA -0.3 VD -0.3 VD18 -0.3 ΔGND (Note 4) IIN - VINA -0.3 VIND -0.3 Ta -40 Tstg -65 Symbol min typ max VA 3.0 3.3 VD 3.0 3.3 VD18 1.7 1.8 VRH VA VRL 0 [AK7780] max Unit 4.3 4.3 2.5 0.3 ±10 mA VA+0.3 VD+0.3 °C 85 °C 150 Unit 3.6 V 3 2007/ ...

Page 12

... ELECTRIC CHARACTERISTICS min (Note 7) 82 (Note 7, Note 8) 88 (Note 7) 88 (Note 9) 90 (Note 10) ±1.85 (Note 11) 1.85 (Note 12 (Note (Note 13) 1.85 ( Note 14 [AK7780] typ max Unit 24 Bits 115 dB 0.1 0.3 dB ±2.00 ±2.15 Vp-p 2.00 2.15 Vp-p 33 kΩ 24 Bits ...

Page 13

... FSO/FSI=48kHz/8kHz Dynamic Range (Input= 1kHz, -60dBFS, A-weighted FSO/FSI=44.1kHz/48kHz Ratio between Input and Output Sample Rate MS0581-E-00-PB Symbol min FSI 7.35 FSO 44.1 -113 -112 -113 -113 -112 110 FSO/FSI 0. [AK7780] typ max Units 24 Bits 96 kHz 96 kHz -103 dB 114 dB 114 dB 114 ...

Page 14

... VIL VOH VOL (Note 16) VOL (Note 17) Iin (Note 18) Iid Iix min (Note 19) (Note 20 min typ max 20%DVDD 30%DVDD DVDD-0.5 0.5 0.4 ± typ max 110 165 1 [AK7780] Unit μA μA μA Unit 2007/09 ...

Page 15

... PR Note 28) SA ΔGD 29 Note 21) min typ max 0 21.5 21.768 24.00 26.5 ±0.005 ±0.01 Note 25) min typ max 0 21.5 21.768 24.00 26.5 ±0.005 ±0.1 [AK7780] Unit kHz kHz kHz kHz dB dB μ Unit kHz kHz kHz kHz dB dB μ 2007/09 ...

Page 16

... Note 30. Measured from the rising edge of SRC_LRCK on the input to the rising edge of LRCLK_O on the output, with there is no phase difference between input and output. MS0581-E-00-PB Range Symbol [AK7780] min typ max 0 0.4583FSI 0 0.4167FSI 0 0.2182FSI 0 0.2177FSI 0 0.1948FSI 0.5417FSI 0.5021FSI 0.2974FSI 0.2812FSI 0.2604FSI ± ...

Page 17

... Unit 11.2896 - MHz 12.288 16.9344 - MHz 18.432 12.4 MHz 18.6 MHz kHz ...

Page 18

... Symbol min tRST (Note 35) tRST tRST tRST tRST - 18 - typ max 128 6.2 typ max 600 600 600 600 600 [AK7780] Unit kHz MHz Unit 2007/09 ...

Page 19

... Symbol min tBLRD 20 (Note 37) tLRBD 20 (Note 37) tBSIDS 40 tBSID [AK7780] max Unit typ max Unit 2007/09 ...

Page 20

... SCLK rise time SCLK frequency SCLK low level width SCLK High level width Microcomputer to AK7780 Time from P_DSPRST , P_ADRST “↓” “↓” Time from RQ “↑” to P_DSPRST , P_ADRST “↑” RQ high level width Time from RQ “↓” to SCLK“↓” ...

Page 21

... Note 39 registered trademark of Philips Semiconductors. MS0581-E-00-PB Symbol Min Typ fSCL tBUF 1.3 tHD:STA 0.6 tLOW 1.3 tHIGH 0.6 tSU:STA 0.6 tHD:DAT 0 tSU:DAT 0 tSU:STO 0.6 tSP [AK7780] Max Unit 400 kHz μs μs μs μs μs μs 0.9 μs μs 0.3 μs 0.3 μ 400 pF 2007/09 ...

Page 22

... Timing Diagram 1) System clock XTI LRCLK_I SRC_LRCK BITCLK_I SRC_BICK 2) RESET NIT_RESET P_CKRST P_ADRST P_DSPRST P_SRCRST MS0581-E-00-PB 1/fXTI 1/fXTI tCR 1/fs tLR 1/fBCLK 1/fBCLK tBR tBCLKH tBCLKL tRST - 22 - [AK7780] tXTI=1/fXTI VIH VIL tCF ts=1/fs VIH VIL tLF tBCLK=1/fBCLK VIH VIL tBF VIL 2007/09 ...

Page 23

... SDOUT * SDIN * SDIN * =SDIN1, SDIN2, SDIN3, SDIN4, SDIN5 SDOUT * =SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUTA1 SRC SRC_LRCK tBLRD SRC_BICK SRCI=SDIN1 MS0581-E-00-PB tMB tMBL tLRBD tBSOD tBSIDS tLRBD tBSIDS - 23 - [AK7780] 50%DVDD 50%DVDD 50%DVDD tBSIDH 50%DVDD 50%DVDD 50%DVDD tBSIDH 50%DVDD 2007/09 ...

Page 24

... Microcontroller interface RQ SCLK ♦ Microcontrollerr AK7780 tREW P_DSPRST P_ADRST RQ tWSC SI SCLK MS0581-E-00-PB tWRF tWRR tSF tSR tSCLKL tSCLKH 1/fSCLK 1/fSCLK tWRQH tSIS tSIH tSCW - 24 - VIH VIL VIH VIL tWRE tWSC tSCW tSCW 2007/09 [AK7780] VIL VIH VIL VIH VIL VIH VIL ...

Page 25

... AK7780 Microcontroller SCLK SO tSOS Note: Timing during the RUN state is identical, except that P_DSPRST and P_ADRST are “H” Bus Interface SDA tBUF tLOW SCL tHD:STA Stop Start MS0581-E-00-PB tSOH tRQHR tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start - 25 - [AK7780] ...

Page 26

... LQFP (Unit 100 1 0.5 0.10 ■ Material & Lead finish Package: Epoxy Lead-frame: Cu Lead-finish: Solder (Pb free) plate MS0581-E-00-PB PACKAGE 16.0±0.3 14 0.22±0.05 0.10 M 1.0 0.5±0 [AK7780] 1.70 Max. 0.20max 0.17±0.05 0°~10° 2007/09 ...

Page 27

... MS0581-E-00-PB MARKING AKM AK7780VT XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7digits) 3) Marking Code: AK7780VT 4) Asahi Kasei Logo IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK7780] in any safety, life support, or ...

Page 28

... Thank you for your access to AKEMD product informations. More detail product informations are available, please contact our sales office or authorized distributors. MS0581-E-00- [AK7780] 2007/09 ...

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