ak4117 AKM Semiconductor, Inc., ak4117 Datasheet - Page 14

• Manufacturer Part Number: ak4117
• Description: Low Power 192khz Digital Audio Receiver
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The AK4117 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down
mode activated by the PWN bit. The RSTN bit initializes the internal registers and timing. The AK4117 should be reset
once at power-up by bringing PDN pin = “L”.
PDN Pin:
RSTN Bit (Address 00H; D0):
PWN Bit (Address 00H; D1):
Two receiver inputs (RX0 and RX1) are available. Each input includes an amplifier for unbalance loads that can accept
350mVpp or greater signal. The IPS bit selects the receiver channel (Table 7). When the UOUTE bit = “1”, the U bit
(user data) can be output from the UOUT pin.
MS0157-E-03
System Reset and Power-Down
Biphase Input
All analog and digital circuits are placed in power-down and reset modes by bringing PDN= “L”. All the registers
are initialized and clocks are stopped. Read/write operations to the registers are disabled.
All the registers except RSTN, PWN, XTL1-0 and EXCK are initialized by bringing RSTN bit = “0”. The internal
timings are also initialized. When RSTN bit= “0”, clocks are output, but SDTO is “L”. All register writes except
RSTN, PWN, XTL1-0 and EXCK are disabled. Reading from the registers is enabled.
Clock recovery mode is initialized by bringing PWN bit = “0”. Clocks from the PLL are stopped while the X’tal
clocks continue to be output. Unlike the PDN pin operation described above, internal registers and mode settings
are not initialized. Read/write operations to the registers are enabled.
UOUT
SDTO
LRCK
(except I
LRCK
(I
2
S)
2
S)
R191
R190
L0
IPS
0
1
L191
Figure 11. UOUT output timing
Table 7. Recovery Data Select
R0
R191
INPUT Data
L1
- 14 -
RX0
RX1
L0
Default
L31
L30
R31
R30
L32
L31
[AK4117]
2004/04