ak4114 AKM Semiconductor, Inc., ak4114 Datasheet - Page 24

• Manufacturer Part Number: ak4114
• Description: High Feature 192khz 24bit Digital Audio Interface Transceiver
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
There are the following eight events who make INT0/1 pin “H”. INT0/1 pin shows the status of following conditions.
Both INT0/1 are fixed to “L” when the PLL is off (CM1,0= “01”). Once the INT0 pin goes to “H”, this pin holds “H” for
1024/fs cycles(this value can be changed by EFH0/1 bits) after those events are removed. INT1 goes to “L” at the same
time when those events are removed. Each INT0/1 pins can mask those eight events individually. Once PAR, QINT and
CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4114 loses lock, registers
regarding C-bit or U-bits are not initialized and keep previous value.
1. Parallel mode
In Parallel Mode, INT0 pin outputs the ORed signal between UNLOCK and PAR, INT1 pin outputs the ORed signal
among AUTO, DTSCD and AUDION. Once INT0 pin goes ”H”, it maintains “H” for 1024/fs cycles after the all error
events are removed. Table 12 shows the state of each output pins when the INT0/1 pin is “H”.
MS0098-E-04
UNLOCK
1. UNLOCK : “1” when the PLL loses lock.
2. PAR
3. AUTO
4. DTSCD
5. AUDION
6. PEM
7. QINT
8. CINT
Error Handling
1
0
0
x
x
x
x
Event (State of Internal Register)
PAR
: “1” when parity error or biphase coding error is detected, and keeps “1” until this register is read.
: “1” when Non-PCM bitstream is detected.
: “1” when DTS-CD bitstream is detected.
: “1” when the “AUDIO” bit in recovered channel status indicates “1”.
: “1” when “PEM” in recovered channel status indicates “1”.
: “1” when Q-subcode differ from old one, and keeps “1” until this register is read.
: “1” when received C bits differ from old one, and keeps “1” until this register is read.
x
1
0
x
x
x
x
AK4114 loses lock when the distance between two preambles is not correct or when those
preambles are not correct.
Updated every sub-frame cycle. Reading this register resets itself.
Updated every 4096 frames cycle.
Updated every DTS-CD sync cycle.
Updated every block cycle.
Updated every block cycle.
Updated every sync code cycle for Q-subcode. Reading this register resets itself.
Updated every block cycle. Reading this register resets itself.
AUTO
x
x
x
1
x
x
0
Table 12. Error Handling (Parallel Mode) x: Don’t care
DTSCD
x
x
x
x
1
x
0
AUDION
x
x
x
x
x
1
0
- 24 -
INT0
“H”
“L”
-
INT1
“H”
“L”
-
Previous Data
Output
SDTO
“L”
Pin
-
Output
Output
“L”
V
-
[AK4114]
2004/03
Output
TX