ak4121 AKM Semiconductor, Inc., ak4121 Datasheet - Page 13

• Manufacturer Part Number: ak4121
• Description: Asynchronous Sample Rate Converter
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
T Internal Reset Function for Clock Change
The internal reset is executed when the input or the output clock are changed. The SDTO is placed “0” during reset.
Within 100ms, the SDTO outputs normal data. When the frequency transition occurs gradually without phase change or
the clock of output port is changed keeping fso/fsi > 4, the internal reset is not executed and the SDTO takes time over
100ms to output normal data. To output normal data within 100ms, please reset by PDN=“L”(refer following section).
T Sequence of changing clocks
The recommended sequence for changing clocks is shown in Figure 6.
Note:
MS0191-E-03
1.
2.
External clocks
(input port
PDN
SDTO
SMUTE (Note2,
Att.Level
(interlal state)
The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN goes
“L”, which will cause the data on SDTO to remain “0”.
SMUTE can also be used to remove the unknown data.
or output port)
recommended)
- dB
0dB
normal data
normal operation
state 1
1024/fso
Figure 6. Sequence of changing clocks
(unknown)
< 10msec
Power
down
Note1
PLL locktime
& fs detection
state 2
- 13 -
< 100msec
1024/fso
normal operation
normal data
[AK4121]
2004/08