hufa76413dk8 Fairchild Semiconductor, hufa76413dk8 Datasheet
hufa76413dk8
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hufa76413dk8 Summary of contents
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... HUFA76413DK8T N-Channel Logic Level UltraFET 60V, 4.8A, 56m General Description These N-Channel power MOSFETs are manufactured us- ® ing the innovative UltraFET process. This advanced pro- cess technology achieves the lowest possible on- resistance per silicon area, resulting in outstanding perfor- mance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low re- verse recovery time and stored charge ...
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... Package Marking and Ordering Information Device Marking Device 76413DK8 HUFA76413DK8T Electrical Characteristics Symbol Parameter Off Characteristics B Drain to Source Breakdown Voltage VDSS I Zero Gate Voltage Drain Current DSS I Gate to Source Leakage Current GSS On Characteristics V Gate to Source Threshold Voltage GS(TH) r Drain to Source On Resistance DS(ON) Dynamic Characteristics ...
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... Figure 3. Normalized Maximum Transient Thermal Impedance 300 TRANSCONDUCTANCE MAY LIMIT CURRENT 100 IN THIS REGION 10V ©2003 Fairchild Semiconductor Corporation T = 25°C unless otherwise noted 100 125 150 Figure 2. Maximum Continuous Drain Current 10V GS ...
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... GATE TO SOURCE VOLTAGE (V) GS Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current ©2003 Fairchild Semiconductor Corporation T = 25°C unless otherwise noted 100 s 1ms 10ms 1 0.1 100 Figure 6. Unclamped Inductive Switching ...
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... C OSS 0V 1MHz DRAIN TO SOURCE VOLTAGE (V) DS Figure 13. Capacitance vs Drain to Source Voltage 150 100 50 0 Figure 15. Switching Time vs Gate Resistance ©2003 Fairchild Semiconductor Corporation T = 25°C unless otherwise noted A 1 250 1.1 1.0 0.9 -80 80 120 160 ...
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... REQUIRED PEAK Figure 16. Unclamped Energy Test Circuit g(REF) Figure 18. Gate Charge Test Circuit Figure 20. Switching Time Test Circuit ©2003 Fairchild Semiconductor Corporation DUT 0.01 Figure 17. Unclamped Energy Waveforms ...
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... The dual die SO-8 package introduces an additional thermal coupling resistance, R Equation 3 describes R B. function of the top copper mouting pad area. R 46.4 21.7 – ln Area = B The thermal coupling resistance vs. copper area is also graphically depicted in Figure 22. ©2003 Fairchild Semiconductor Corporation , and the JM 300 , application’s ambient o 250 ( C/ never exceeded. ...
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... PSPICE Electrical Model .SUBCKT HUFA76413DK8T 7.8e- 9.8e-10 CIN 6 8 5.8e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 67.4 EDS EGS ESG EVTHRES EVTEMP GATE LDRAIN 2 5 1e-9 LGATE ...
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... SABER Electrical Model REV April 2002 template HUFA76413DK8T n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 8e-13 1.58e-2, trs1 = 1e-3, trs2 = 3e-6, xti = 3.2, cjo = 8e-10 3.2e- 0.54) dp..model dbreakmod = (rs = 1.18, trs1 = 2e-3, trs2 = -2.6e-5) dp..model dplcapmod = (cjo = 5.7e-10, isl =10e-30, nl =10 0.87) m..model mmedmod = (type=_n, vto = 1.68 =1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.05 35 1e-30, tox = 1) m ...
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... CTHERM8 RTHERM1 th 8 3.5e-2 RTHERM2 8 7 6.0e-1 RTHERM3 RTHERM4 RTHERM5 RTHERM6 RTHERM7 RTHERM8 SABER Thermal Model SABER thermal model HUFA76413DK8T 2 Copper Area = 0.493in template thermal_model th tl thermal_c th ctherm.ctherm1 th 8 =8.5e-4 ctherm.ctherm2 8 7 =1.8e-3 ctherm.ctherm3 7 6 =5.0e-3 ctherm.ctherm4 6 5 =1.3e-2 ctherm ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet Series™ ® Bottomless™ FAST CoolFET™ FASTr™ ...