hufa76504dk8 Fairchild Semiconductor, hufa76504dk8 Datasheet - Page 7

• Manufacturer Part Number: hufa76504dk8
• Description: 2.3a, 80v, 0.222 Ohm, Dual N-channel, Logic Level Ultrafet Power Mosfet
• Manufacturer: Fairchild Semiconductor

Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
an application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 23
defines the R
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are R
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. R
times a cofficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
©2001 Fairchild Semiconductor Corporation
R
P
1. Mounting pad area onto which the device is attached and
2. The number of copper layers and the thickness of the
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
DM
DM
JA
whether there is copper on one side or both sides of the
board.
board.
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
.
=
=
------------------------------ -
T
103.2 24.3
JM
R
JA
–
T
–
JA
A
A
JA
(
for the device as a function of the top
o
C), and thermal resistance R
is defined as the natural log of the area
ln
Area
JA
values listed in the
JM
is never exceeded.
JM
DM
, and the
JA
is complex
DM
(
o
C/W)
(EQ. 2)
(EQ. 1)
, in
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFET™s are offered with
two die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance,
function of the top copper mounting pad area.
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (R
(
inches of copper:
R
R
T
die. Similarly, P
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70°C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calulate T
calulate T
.
T
T
T
T
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
R
T
T
R
J1
J1
J1
J2
J2
J1
J2
JA1
1
= 119°C
= 150°C
and T
= (0 Watts)(159°C/W) + (0.5 Watts)(97°C/W) + 70°C
= (0.5 Watts)(159°C/W) + (0 Watts)(97°C/W) + 70°C
300
250
200
150
100
) are equivalent for both die. For example at 0.1 square
=
=
=
50
=
0
= R
P
P
0.001
46.4 21.7
R
1
2
R
R
J2
J2
JA2
–
2
.
R
JA
JA
define the junction temerature of the respective
= 97°C/W
R
1
+
+
= 159°C/W
JA
= 46.4 - 21.7
AREA, TOP COPPER AREA (in
P
P
and P
= 103.2 - 24.3
2
1
ln
R
R
R
JA
Area
2
0.01
+
+
228
. Equation 3 describes
define the power dissipated in each
) and thermal coupling resistance
T
T
A
A
*
o
J1
ln
C/W - 0.006in
*
(AREA)
and and Equation 5 to
ln
(AREA)
191
2
o
C/W - 0.027in
0.1
2
) PER DIE
R
Rev. A, June 4, 2001
2
as a
(EQ. 3)
(EQ. 4)
(EQ. 5)
1