73k224bl ETC-unknow, 73k224bl Datasheet - Page 19
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73k224bl
Manufacturer Part Number
73k224bl
Description
Single-chip Modem Integrated Hybrid
Manufacturer
ETC-unknow
Datasheet
1.73K224BL.pdf
(33 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
73k224bl-IH
Manufacturer:
TERIDIAN
Quantity:
229
SPECIAL REGISTER
NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a one and addressing CR3. This
ADDR
BIT
D7, D4, D0
D6
D5
D3
D2, D1
101
SR
register provides functions to the 73K224BL user that are not necessary in normal communications.
Bits D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6
must be returned to a zero.
D7
0
TXBAUD CLK
Signal Quality
RXUNDSCR
TXD Source
Level Select
D2
0
0
1
1
TXBAUD
NAME
CLOCK
Data
D6
D1
0
1
0
1
DESCRIPTION
Not used at this time. Only write zeros to these bits.
TXBAUD clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUD signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXDALT bit, CR3 bit D7, should have data
transitions that start 1/2 bit period delayed from the TXBAUD clock edges.
This bit outputs the data received before going to the descrambler.
This is useful for sending special unscrambled patterns that can be used for
signaling.
This bit selects the transmit data source; either the TXD pin if zero or the
TXDALT if this bit is a one. The transmit pattern bits D7 and D6 in CR1
override either of these sources.
The signal quality indicator is a logical zero when the signal received is
acceptable for low error rate reception. It is determined by the value of the
mean squared error (MSE) calculated in the decisioning process when
compared to a given threshold. This threshold can be set to four levels of
error rate. The SQI bit will be low for good or average connections. As the
error rate crosses the threshold setting, the SQI bit will toggle at a 1.66 ms
rate. Toggling will continue until the error rate indicates that the data pump
has lost convergence and a retrain is required. At that point the SQI bit will be
a one constantly. The SQI bit and threshold selection are valid for QAM and
DPSK only and indicates typical error rate.
THRESHOLD VALUE
RXUN-
DSCR
DATA
D5
Single-Chip Modem w/ Integrated Hybrid
10
10
10
10
-5
-6
-4
-3
D4
0
19
V.22bis/V.22/V.21/Bell 212A/103
SOURCE
TXD
D3
UNITS
BER (default)
BER
BER
BER
SELECT 1
QUALITY
SIGNAL
LEVEL
D2
SELECT 0
QUALITY
SIGNAL
LEVEL
73K224BL
D1
D0
0