ispgal22lv10 Lattice Semiconductor Corp., ispgal22lv10 Datasheet - Page 9

• Manufacturer Part Number: ispgal22lv10
• Description: In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
High Z to Active High at 1.9V
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
f
max with External Feedback 1/(
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
L O G I C
A R R A Y
LOGIC
ARRAY
t
su +
f
max with No Feedback
t
s u
t
h
REGISTER
R EG I S T E R
CLK
C L K
1.5ns 10% – 90%
50
50
50
50
50
t
GND to 3.0V
R
See Figure
su+
t
c o
1
1.5V
1.5V
t
co)
35pF
35pF
35pF
35pF
35pF
C
L
9
Specifications ispGAL22LV10
*C
FROM OUTPUT (O/Q)
UNDER TEST
L
includes test fixture and probe capacitance.
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
f
max with Internal Feedback 1/(
LOGIC
ARRAY
TEST POINT
Z
t
cf
0
t
pd
= 50 , C
REGISTER
CLK
L
= 35pF*
t
su+
t
+1.45V
cf)
R
1