ml7041 Oki Semiconductor, ml7041 Datasheet
ml7041
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ml7041 Summary of contents
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... Audio CODEC GENERAL DESCRIPTION The ML7041 is a single-channel full duplex CODEC LSI device which performs mutual transcoding between the analog voice band signals ranging from 300 to 3400 Hz and the 64 kbps PCM serial data. Provided with such functions as DTMF Tone generation, transmit/receive data gain control, side-tone path, and low-dropout regulator, the ML7041 is best suited for telephone terminals in digital wireless systems ...
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... CR1-B1 CR0-B2 CR4-B6 Slope BPF A/D Filter CR3-B7,6,5 CR3-B3,2,1,0 LPF D/A CR2-B2,1,0 Sign bit 20 k CR1-B5,4 MCU I FEDL7041-04 ML7041 CR0-B0 PCM Com-p PCMOUT and BCLK TONE/DTMF Gen SYNC CR0-B0 PCM PCMIN Expand Regulator1 RG1IN (3.6 V) (150 mA) RG1O (3.0 V) RG1PDN (3.0 V/0 V) Regulator2 RG2IN (3.6 V) (150 mA) RG2O (3 ...
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... OKI Semiconductor PIN CONFIGURATION (TOP VIEW EAR2O 2 EAR1O EXTO 5 EXTI SPO– 8 AG2 9 AG3 10 SPO 48-Pin Plastic TQFP FEDL7041-04 ML7041 36 RG2IN 35 RG2O 34 AGR2 33 RG1IN 32 RG1O AGR1 31 RG2PDN 30 29 RG1PDN PDN 28 27 SYNC 26 BCLK 25 DG 3/28 ...
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... MIC3– I Transmit side amplifier 3 inverting input 47 MIC3O O Transmit side amplifier 3 output Analog signal ground (1.4 V) Description State in power-down mode FEDL7041-04 ML7041 — High impedance High impedance — High impedance — — High impedance — — High impedance — — High impedance ...
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... CR1-B5 and CR1-B4. If the amplifiers connected to EAR1O and EAR2O are not being selected, the amplifiers are deactivated and their outputs are put into high impedance state. Gains of output levels of the pins can be adjusted using the external resistors. The power control is accomplished by CR0-B6. Refer to Figure 1. load. load. The receive side FEDL7041-04 ML7041 5/28 ...
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... MIC3+ R6 MIC3O SG VREF EAR1O D/A EAR2O EXTO R7 EXTI R8 SPO– SPO+ Figure 1 Analog Interface FEDL7041-04 ML7041 Transmit Gain : V /Vi = (R2/R1) MIC1O : V /Vi = (R4/R3) MIC2O : V /Vi = (R6/R5) MIC3O Input select :CR1-B7, B6 “00” -> MIC1 :CR1-B7, B6 “01” -> MIC2 :CR1-B7, B6 “10” -> MIC3 :CR1-B7, B6 “11” -> no-input ...
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... GND, and tantalum bypass capacitor must be connected from the output pin to GND. Note1: The RG1O and RG2O outputs must not be used as the 3 V supply for the ML7041. Note2: The RG1IN and RG2IN should be common near the device and supplied from the same power supply. ...
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... Refer to Figure 2. SYNC BCLK PCMIN or PCMOUT MSB Figure 2 PCM Interface Basic Timing Diagram 8 kHz (125 µs) LSB * 14 bits when linear mode is selected (a) Long frame synchronous interface 8 kHz (125 µs) LSB * 14 bits when linear mode is selected (b) Short frame synchronous interface FEDL7041-04 ML7041 8/28 ...
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... A register data write register address write 2 C Interface Read Timing: read-back mode A Acknowledged (ML7041 drive SDA to “0”) A Not Acknowledged Don’t care (“0” or “1”) FEDL7041-04 ML7041 register data A P ...
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... GAIN0 ON/OFF GAIN3 TONE — TONE4 TONE3 TONE2 TONE1 TONE0 R/W SEND — RG2PDN RG1PDN GP4C — — — — — NOISE0 R: Read only register FEDL7041-04 ML7041 SLP SLP SEL LNR R/W SW — RX PAD R/W C R/W GAIN2 GAIN1 GAIN0 TONE TONE ...
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... CLK T SYNC BCLK SB T BCLK SYNC BS t SYNC WS (average) is less than 105 C. jmax ja = 195 C (not mounted on a PCB, in still-air-ambient 156 C (mounted on a typical PCB, in still-air-ambient) FEDL7041-04 ML7041 Rating Unit –0.3 to +4.6 V –0 +0 –0 +0 –55 to +150 C +150 C Min. ...
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... THD = 1% DD EAR1O, EAR2O, SPO+, SPO– 3 MIC1O, MIC2O, MIC3O EAR1O, EAR2O, SPO+, SPO–, EXTO SG SG All internal analog switches (1 bias) PP FEDL7041-04 ML7041 = 2 –40 to +85 C) Min. Typ. Max. Unit 0 5.0 11 16 — — ...
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... FEDL7041-04 ML7041 = 2 – Min. Typ. Max. Unit 25 — — dB –0.15 — 0.20 dB Reference dB –0.15 — 0. — 0. — ...
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... Figure 6 t 100 pF XD2 t RD2 t XD3 t RD3 f SCL t BUF t LOW CL = See t — HIGH 50 pF Figure 7 FEDL7041-04 ML7041 (V = 2 – Min. Typ. Max. Unit — — –68 dBmOp — — –72 0.320 0.285 0.359 Vrms *3 0.320 0.285 0.359 Vrms ...
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... RH RL Condition All gain stages, to programmed D G value Condition Silence Voice VON (Voice/silence differential: 10 dB) VOF For detection level set values by VX CR6-B6 FEDL7041-04 ML7041 (V = 2 – Min. Typ. Max. Unit –1.5 — +1.5 % –18 –16 –14 dBm0 –16 – ...
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... OUT I 3.5 V < RGIN < 4 150 mA , RGIN = 3.6 V DROP OUT OUT / 3.3 V < RGIN < 4 RG1PDN = 0, RG2PDN = 0 FEDL7041-04 ML7041 (V = 2 – Min. Typ. Max. Unit — — 0 — — 2 – Min ...
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... WS t XD2 XD2 MSB RD2 RD2 MSB Figure 6 PCM Interface Timing FEDL7041-04 ML7041 XD3 LSB . XD1 . SDX XD3 LSB RD3 LSB RD3 ...
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... OKI Semiconductor Interface SDA t BUF t LOW SCL t HD:STA SCL SU:STA HD:DAT HIGH SU:DAT 2 Figure Interface Timing FEDL7041-04 ML7041 t HD:STA t SU:STO Sr P 18/28 ...
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... A-law 0: Power on 1: Power down 0: Power on 1: Power down 0: Power on 1: Power down 0: Slope filter disable 1: Slope filter enable 0: CASE1 1: CASE2 1000 1500 2000 2500 Frequency [Hz] FEDL7041-04 ML7041 SLP SLP LNR SEL Power down 1: Power on CASE1 ...
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... Short frame synchronous interface 0: The SWB pin is internally connected to the SWA pin. 1: The SWB pin is internally connected to the SWC pin. The unconnected pins high impedance state pad 1: A pad loss is inserted in the receive side voice path. FEDL7041-04 ML7041 — ...
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... FEDL7041-04 ML7041 GAIN2 RX GAIN1 RX GAIN0 Receive Gain 0 – – – – ...
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... FEDL7041-04 ML7041 TONE TONE TONE GAIN2 GAIN1 GAIN0 Tone Generator Gain 0 – – – – – – ...
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... 480 667 800 1000 FEDL7041-04 ML7041 TONE2 TONE1 TONE0 DTMF B1 B0 Frequency 0 0 852 Hz + 1209 852 Hz + 1336 852 Hz + 1477 852 Hz + 1633 ...
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... –– –– –– OFF Noise –– –– Level0 silence 1: voice detect FEDL7041-04 ML7041 GP3C GP2C GP1C –– –– –– –– ...
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... µ Voice detect A/D Slope BPF Filter D/A LPF 20 k Sign bit MCU I Speaker FEDL7041-04 ML7041 PCM PCMOUT Com- pand BCLK TONE/DTMF SYNC Gen V (3 PCMIN PCM Expand RG1IN(3.6 V) Regulator1 Other (150 mA) IC RG1O(3 RG1PDN C=10µF RG2IN(3 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7041-04 (Unit: mm) Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ( 5µm) Package weight (g) 0.13 TYP. Rev. No./Last Revised 4/Oct. 28, 1996 ML7041 26/28 ...
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... FEDL7041-03 Nov. 2, 2005 FEDL7041-04 Mar. 2, 2006 Page Previous Current Edition Edition st ― ― 1 Edition 8 8 More clarification of PCMOUT output state 11 11 Addition of t Addition Addition of description about Addition of description about CR6-B3 FEDL7041-04 ML7041 Description SB SB and t XD1 SDX 27/28 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL7041-04 Copyright 2006 Oki Electric Industry Co., Ltd. ML7041 28/28 ...