ml7084-001 Oki Semiconductor, ml7084-001 Datasheet
ml7084-001
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ml7084-001 Summary of contents
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... OKI Semiconductor ML7224-001TC 4ch VoIP CODEC GENERAL DESCRIPTION The ML7224-001 is a VoIP codec that has speech codecs with four channels. These speech codecs support the PLC (Packet Loss Concealment) function, with the coding format selectable between G.711 (μ-law) and G.711 (A-law). The ML7224-001 is equipped with an echo canceller that supports a delay for each channel ...
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... OKI Semiconductor • Dial pulse transmission function (One block installed per channel input/output port • 16-bit timer (One block installed for every two channels.) • Equipped with an interface for serial control • Allows downloading of DSP firmware • General-purpose input/output port: 28 ports (some of them have a secondary function) • ...
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... OKI Semiconductor BLOCK DIAGRAM PCM CODEC(CH0 a) ITS0Ua G.711 PCMI_a S /P ITS0La u-law pia SYNC G .711 ITS0_SEL_a A-law BCLK PCM_SEL[1:0]_a CLKSEL OTS0_SEL _a G.711 u-law OTS0Ua PCMO_a P /S G.711 OTS0La poa A-law GSX0 _a 10kΩ AIN0N_a A/D0a BPF AIN0P _a AMP 0Ta CH0_IFSEL_a STGAIN _CH0a ...
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... OKI Semiconductor PIN ASSIGNMENT (TOP VIEW) AVDD0 133 AGND0 134 AIN0P_a 135 N.C. 136 AIN0N_a 137 N.C. 138 GSX0_a 139 N.C. 140 VFRO0_a 141 N.C. 142 AIN1P_a 143 N.C. 144 AIN1N_a 145 N.C. 146 GSX1_a 147 N.C. 148 VFRO1_a 149 N.C. 150 AVREF 151 N.C. 152 AIN0P_b 153 N.C. 154 AIN0N_b 155 N ...
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... OKI Semiconductor PIN DESCRIPTIONS MCU Interface Pin No. Symbol I/O 100 D0_a I/O 101 D1_a I/O 102 D2_a I/O 103 D3_a I/O 104 D4_a I/O 105 D5_a I/O 106 D6_a I/O 107 D7_a I/O 108 D8_a I/O 109 D9_a I/O 110 D10_a I/O 111 D11_a I/O 112 D12_a I/O 113 D13_a I/O 114 D14_a I/O 115 D15_a I/O 89 A0_a ...
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... OKI Semiconductor MCU Interface (continued) Pin No. Symbol I/O 33 D0_b I/O 32 D1_b I/O 31 D2_b I/O 30 D3_b I/O 29 D4_b I/O 28 D5_b I/O 27 D6_b I/O 26 D7_b I/O 25 D8_b I/O 24 D9_b I/O 23 D10_b I/O 22 D11_b I/O 21 D12_b I/O 20 D13_b I/O 19 D14_b I/O 18 D15_b I/O 44 A0_b I 43 A1_b I 42 A2_b I 41 A3_b I 40 A4_b I 39 A5_b I 38 A6_b I 37 A7_b I 12 CSB_b I 13 ...
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... OKI Semiconductor FRAM/DMA Interface Pin No. Symbol I/O 126 ACK0B_a I 125 ACK1B_a I FR0B_a 124 O (DMARQ0B_a) FR1B_a 123 O (DMARQ1B_a) 7 ACK0B_b I 8 ACK1B_b I FR0B_b 9 O (DMARQ0B_b) FR1B_b 10 O (DMARQ1B_b) When PDNB = “0” Transmit buffer DMA access acknowledge signal input for I CH0a/CH1a Receive buffer DMA access acknowledge signal input for ...
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... OKI Semiconductor Interrupt Pin No. Symbol I/O 122 INTB_a O 11 INTB_b O Analog Interface Pin No. Symbol I/O 135 AIN0P_a I 137 AIN0N_a I 139 GSX0_a O 141 VFRO0_a O 143 AIN1P_a I 145 AIN1N_a I 147 GSX1_a O 149 VFRO1_a O 153 AIN0P_b I 155 AIN0N_b I 157 GSX0_b O 159 VFRO0_b O 161 AIN1P_b I 163 AIN1N_b ...
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... OKI Semiconductor Power Down Control Pin No. Symbol I/O 75 PDNB I PCM Interface Pin No. Symbol I/O 67 PCMO_a O 69 PCMI_a I 66 PCMO_b O 68 PCMI_b I 70 BCLK I/O 71 SYNC I/O 76 CLKSEL I Serial Control Interface Pin No. Symbol I/O 63 SDO_a O 65 SDI_a I 77 SCLK_a I 78 SDENB_a I 62 SDO_b O 64 SDI_b I 60 SCLK_b ...
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... OKI Semiconductor General-Purpose Input/Output Ports Pin No. Symbol I/O 131 GPIOA0_a I/O 132 GPIOA1_a I/O 127 GPIOB0_a I/O 128 GPIOB1_a I/O 129 GPIOB2_a I/O 130 GPIOB3_a I/O 79 GPIOC0_a I/O 80 GPIOC1_a I/O 81 GPIOC2_a I/O 82 GPIOC3_a I/O 83 GPIOC4_a I/O 84 GPIOC5_a I/O 85 GPIOC6_a I/O 86 GPIOC7_a I/O 2 GPIOA0_b I/O 1 GPIOA1_b I/O 6 GPIOB0_b I/O 5 GPIOB1_b I/O 4 GPIOB2_b I/O 3 GPIOB3_b I/O 58 GPIOC0_b I/O 57 GPIOC1_b I/O 56 GPIOC2_b I/O 55 GPIOC3_b I/O 54 GPIOC4_b I/O 53 GPIOC5_b I/O 52 GPIOC6_b I/O 51 GPIOC7_b ...
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... OKI Semiconductor Analog Power Supply Pins Pin No. Symbol I/O ⎯ 133 AVDD0 ⎯ 170 AVDD1 ⎯ 134 AGND0 ⎯ 169 AGND1 Digital Power Supply Pins Pin No. Symbol I/O ⎯ 16 DVDD0 ⎯ 35 DVDD1 ⎯ 45 DVDD2 ⎯ 73 DVDD3 ⎯ 98 DVDD4 ⎯ 117 DVDD5 ⎯ 175 DVDD6 ⎯ ...
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... OKI Semiconductor Test Pins Pin No. Symbol I/O 88 TST0 I 87 TST1 I 50 TST2 I 48 TST3 I N.C. Pins Pin No. Symbol I/O ⎯ 136 N.C. ⎯ 138 N.C. ⎯ 140 N.C. ⎯ 142 N.C. ⎯ 144 N.C. ⎯ 146 N.C. ⎯ 148 N.C. ⎯ 150 N.C. ⎯ 152 N.C. ⎯ 154 N.C. ⎯ 156 N.C. ⎯ 158 N.C. ⎯ ...
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... OKI Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol Analog power supply AVDD voltage Digital power supply voltage DVDD Analog input voltage VAIN VDIN1 Digital input voltage VDIN2 Output current IO Power dissipation PD Storage temperature range Tstg RECOMMENDED OPERATING CONDITIONS (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) ...
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... OKI Semiconductor ELECTRICAL CHARACTERISTICS DC Characteristics (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter Symbol (PDNB = “0”, DVDD = AVDD = 3.3 V, ISS Power supply current IDD PCM interface used; analog interface Digital input pin IIH input leakage current ...
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... OKI Semiconductor This page intentionally left blank. FEDL7224-001FULL-01 ML7224-001TC 15/225 ...
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... OKI Semiconductor This page intentionally left blank. FEDL7224-001FULL-01 ML7224-001TC 16/225 ...
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... OKI Semiconductor AC Characteristics Gain Setting (Speech CODEC = G.711 (μ-law)) (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter Symbol Transmit and receive GAC gain setting accuracy Tone Output (Speech CODEC = G.711 (μ-law)) (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60° ...
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... OKI Semiconductor PDNB, XO, AVREF Timings (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter Symbol Power down signal pulse tPDNB width AVDD supply delay time tAVDDON Oscillation start-up time txtal AVREF rise time tAVREF DVDD AVDD ...
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... OKI Semiconductor PCM Interface (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter Symbol Bit clock frequency fBCLK Bit clock duty ratio dBCLK Sync signal frequency fSYNC Sync signal duty ratio dSYNC1 Transmit/receive signal sync timing ...
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... OKI Semiconductor BCLK tBS tSB tWS SYNC tXD1 tXD 2 MSB PCMO tSDX Figure 4 PCM Interface Output Timing (Long Frame) BCLK tBS tSB tWS SYNC tXD1 tXD 2 MSB PCMO Figure 5 PCM Interface Output Timing (Short Frame ...
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... OKI Semiconductor Control Register Interface (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter Address setup time (during read) Address hold time (during read) Address setup time (during write) Address hold time (during write) Write data setup time ...
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... OKI Semiconductor Transmit and Receive Buffer Interface (in Frame Mode) (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter FR1B setup time FR1B output delay time Address setup time (during read) Address hold time (during read) Address setup time (during write) ...
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... OKI Semiconductor Transmit and Receive Buffer Interface (in DMA Mode) (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter DMARQ1B setup time DMARQ1B output delay time Address setup time (during read) Address hold time (during read) Address setup time (during write) ...
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... OKI Semiconductor DMARQ0B Output DMARQ1B Output tDR1S A7-A0 Input D15-D0 Input/output ACK0B Input ACK1B Input WRB Input RDB Input Figure 8 Transmit and Receive Buffer Interface (in DMA Mode) tDR0S tDR1FD tDR1RD A1 tWAS tWAH tRAS D1 Input tWDS tWDH tAK0S tAK1S tAK1H tAD tWW Write timing ...
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... OKI Semiconductor Serial Control Interface (Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD = 3.0 to 3.6 V, AGND = DGND = 0 −20 to +60°C) Parameter Symbol Serial control interface timing ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts8 ts9 ts10 ts11 Write Control SDENB ts1 SCLK ts2 ...
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... OKI Semiconductor PIN FUNCTIONAL DESCRIPTIONS D0_a–D15_a Data input/output pins for accessing the frames/DMA/control registers for CH0a/CH1a. Since these are input/output pins, connect a pull-up resistor. If 8-bit bus access is selected with the MCU interface data width selection register (BW_SELa), D0–D7 will be enabled. If they are used for 8-bit bus access (BW_SELa = “1”), upper D8–D15 will always be placed in an input state ...
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... OKI Semiconductor ACK0B_a This is the DMA acknowledge input pin for the DMARQ0B_a signal during DMA access of the transmit buffer of CH0a/CH1a and becomes valid in the DMA mode (FD_SELa = “1”). Tie this pin to “1” when using this LSI in the frame mode (FD_SELa = “0”). ...
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... OKI Semiconductor ACK0B_b This is the DMA acknowledge input pin for the DMARQ0B_b signal during DMA access of the transmit buffer of CH0b/CH1b and becomes valid in the DMA mode (FD_SELb = “1”). Tie this pin to “1” when using this LSI in the frame mode (FD_SELb = “0”). ...
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... OKI Semiconductor AIN0N_a, AIN0P_a, GSX0_a Transmission analog input and transmission level adjustment pins for CH0a. AIN0N_a is connected to the inverting input pin of the internal transmit amplifier, and AIN0P_a is connected to the non-inverting input pin. GSX0_a is conneced to the output pin of the internal transmit amplifier. For more information about level adjustment, see Figure 10. At hardware power down (PDNB = “ ...
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... OKI Semiconductor AIN0N_b, AIN0P_b, GSX0_b Transmission analog input and transmission level adjustment pins for CH0b. AIN0N_b is connected to the inverting input pin of the internal transmit amplifier, and AIN0P_b is connected to the non-inverting input pin. GSX0_b is conneced to the output pin of the internal transmit amplifier. For more information about level adjustment, see Figure 10. At hardware power down (PDNB = “ ...
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... OKI Semiconductor C1 Out : Max 1.3Vp-p C3 Out : Max 1.3Vp-p C5 Out : Max 1.3Vp-p C7 Out : Max 1.3Vp-p C9 2.2 to 4.7μF GSX0_a R2 10kΩ R1 AIN0N_a AIN0P_a AMP0T_a VFRO0_SEL_a 10kΩ C2 VFRO0_a AMP0R_a GSX1_a R4 10kΩ R3 AIN1N_a AIN1P_a AMP1T_a VFRO1_SEL_a C4 10kΩ VFRO1_a AMP1R_a GSX0_b R6 10kΩ ...
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... OKI Semiconductor XI, XO These are the pins for either connecting the crystal oscillator for the master clock or for inputting an external master clock signal. The oscillations of the master clock oscillator will be stopped during a power down due to the PDNB signal. The oscillations start when the power down condition is released, and the internal clock supply of the LSI will be started after counting up the oscillation stabilization period (of about 10 ms), and the DSP firmware can then be downloaded ...
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... OKI Semiconductor PCMO_a PCM signal output pin for CH0a/CH1a. It outputs a PCM signal in synchronization with the rise of BCLK or SYNC. Regarding output from PCMO_a, data will be output only in the applicable time slot segment according to the setting of the selected time slot position, and the output will high impedance state in any other segments. ...
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... OKI Semiconductor CLKSEL Input/output control input pin of SYNC and BCLK. When set to “0”, this pin is configured as input, and when set to “1” configured as output. SDO_a Serial control output pin for CH0a/CH1a. If the serial control function of CH0a/CH1a is not used (SCNTEN = “0”), SDO_a will be placed in a high impedance state ...
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... OKI Semiconductor GPIOA[1:0]_a General-purpose input/output port A[1:0] for CH0a/CH1a. As the secondary functions of GPIOA[1:0]_a, the dial pulse output pin for CH1a (DPO1a) and the dial pulse output pin for CH0a (DPO0a) are assigned. For unused general-purpose input/output ports, fix inputs at either “0” or “1”. ...
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... OKI Semiconductor FUNCTIONAL DESCRIPTION MCU Interfaces (1) Overview This LSI has two MCU interfaces: one for CH0a/CH1a and the other for CH0b/CH1b. Each MCU interface consists of control registers, transmit and receive buffers, frame and DMA controllers that control access to the transmit and receive buffers, and a DSP firmware downloader. ...
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... OKI Semiconductor (3) Transmit and Receive Buffers A. Number of embedded transmit and receive buffers This LSI is embedded with two systems of transmit and receive buffers: TX-FIFOa/RX-FIFOa for CH0a/CH1a, and TX-FIFOb/RX-FIFOb for CH0b/CH1b. B. Control parameters of transmit and receive buffers Table 2 lists the controllable parameters of the transmit and receive buffers. ...
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... OKI Semiconductor D. Structure of Transmit and Receive Buffers Examples of timings of accessing the transmit and receive buffers are shown in Figure 13. Although both the transmit and the receive buffers have a double buffer structure, the buffer to be accessed from the MCU side is automatically switched at every buffering time or by the completion of reading or writing of the specified number of words ...
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... OKI Semiconductor F. Data Storage Format The data storage formats for the transmit and receive buffers are shown in Figure 14. 1) G.711 (64 kbps) G.711(64 kbps, μ-law/A-law) 8 bits/125 μs Buffer configuration 80 samples /10 ms 160 samples /20 ms PCM coding configuration bit7 bit6 Word configuration ...
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... OKI Semiconductor (4) Frame/DMA Access As for access to the transmit and receive buffers, either the frame mode or DMA mode can be selected. Select access to the transmit and receive buffers for CH0a/CH1a (TX-FIFOa/RX-FIFOa) with the FRAME/DMA selection register_a (FD_SELa), and the transmit/receive buffer for CH0b/CH1b (TX-FIFOb/RX-FIFOb) with the FRAME/DMA selection register_b (FD_SELb) ...
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... OKI Semiconductor A. When in the Frame Mode (FRAME/DMA selection register_a (FD_SELa) = “0”) The control timing of the transmit buffer and the method of accessing it during the frame mode are shown in Figure 15. When the transmit buffer, which stores the compressed speech data of the transmitting side (the speech compressing side), becomes full, FR0Ba goes to a “ ...
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... OKI Semiconductor B. When in the DMA mode (FRAME/DMA selection register_a (FD_SELa) = “1”) The transmit buffer control timing during the DMA mode is shown in Figure 17. When the transmit buffer, which stores the compressed speech data of the transmitting side (the speech compressing side), becomes full, DMARQ0Ba goes to a “ ...
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... OKI Semiconductor (5) DSP Firmware Download Function A. Overview This LSI has internal registers for downloading the DSP firmware: DLCR0a–DLCR5a on the DSP_A side, and DLCR0b–DLCR5b on the DSP_B side. Download the DSP firmware by accessing these registers via a parallel bus interface or serial control interfaces. ...
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... OKI Semiconductor Wait for more *4 DSP_RESET_ b ( CR0b_ B7 Download mode DLb_EN (DLCR0 b_B0 PRAM data write processing DRAM data write processing DL_ENb (DLCR0 b_B0 DSP_RESET_b (CR0b_B Timer T0b start Yes Has timer T0b expired ? * DLb_ST0 =1 ? Yes NO DL_ST[2 :1]_b = 00b? ...
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... OKI Semiconductor Start of DSP_A side PRAM data write DLa_ SEL (DLCR0 a_B1 DLa_ AD0 (DLCR1a) = 00h DLa_ AD1 (DLCR2a) = 00h DLa_ BUF0 (DLCR3a) = XXh DLa_ BUF1 (DLCR4a) = XXh DLa_ BUF2 (DLCR5a) = XXh NO Writing 20,480 words complete ? Yes End of DSP_A side PRAM data write ...
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... OKI Semiconductor Control Methods of Transmit and Receive Buffers There are four operating states of a speech codec, depending on the settings in the following two registers: • Speech codec-CH0 control register (SC_CH0EN) • Speech codec-CH1 control register (SC_CH1EN) The four oparting states are “stop state,” “single-channel operating state-CH0,” “single-channel operating state-CH1,” ...
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... OKI Semiconductor (1) G.711 (μ-law/A-law mode: single-channel operation (CH0) Figure 22 G.711 (μ-law/A-law Mode: Control Timing of Single-Channel Operation (CH0) FEDL7224-001FULL-01 ML7224-001TC 47/225 ...
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... OKI Semiconductor Operational Description [Transmitting side] 1) Activated Set DEC_OUTON to “0” and SC_CH0EN “0” → “1” The speech codec is activated within a maximum of 250 μs after SC_CH0EN has been set to "1". The encoder is activated in the already initialized condition and starts encoding the CH0 transmit data immediately after the speech codec is activated ...
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... OKI Semiconductor 2) Operating The data written by the MCU in the valid write period WE_SCn is output in decode output segment Rn_CH0. This operation is repeated until stopping ...) 3) Stop Set SC_CH0EN “1” → “0” and DEC_OUTON “1” → “0”. ...
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... OKI Semiconductor (2) G.711 (μ-law/A-law mode: single-channel operation (CH1) Figure 23 G.711 (μ-law/A-law Mode: Control Timing of Single-Channel Operation (CH1) FEDL7224-001FULL-01 ML7224-001TC 50/225 ...
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... OKI Semiconductor Operational Description [Transmitting side] 1) Activated DEC_OUTON “0”, SC_CH1EN “0” → “1” The speech codec is activated within a maximum of 250 μs after SC_CH1EN has been set to "1". The encoder is activated in the already initialized condition and starts encoding the CH1 transmit data immediately after the speech codec is activated ...
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... OKI Semiconductor 2) Operating The data written by the MCU in the valid write period WE_SCn is output in decode output segment Rn_CH1. This operation is repeated until stopping ...) 3) Stop Set SC_CH1EN “1” → “0”, DEC_OUTON “1” → “0”. Decoding after stop is invalid. ...
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... OKI Semiconductor (3) G.711 (μ-law/A-law mode: 2-channel processing upon and after activation Figure 24 G.711 (μ-law/A-law Mode: Control Timing of 2-Channel Processing upon and after Activation FEDL7224-001FULL-01 ML7224-001TC 53/225 ...
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... OKI Semiconductor Operational Description 1) 2-channel operation activated To activate a 2-channel operation from the stop state of a speech codec, set both SC_CH0EN and SC_CH1EN to “1” at the same time. Encoder: Starts encoding transmit data of CH0 and CH1 within a maximum of 250 μsec after SC_CH0EN and SC_CH1EN are set to “ ...
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... OKI Semiconductor The following describes the operation when receive data is written in the order of CH0 to CH1. Write CH0 receive data (80 bytes) by the first receive data write request (FR1 = 1&RXREQ_First = 1). Also, before starting to write CH0 receive data, by setting the receive data write channel notification register (RXFLAG) to “ ...
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... OKI Semiconductor WE_DC1 (CH0 & CH1) There is no time limit for the first valid write period after starting a speech codec (CH0 & CH1). If only the tWAIT wait time has elapsed after completion of writing received data of CH0 and CH1, the decode output control register (DEC_OUTON) can be set to “1”. The decoder starts decode output the tDECON time after DEC_OUTON is set to “ ...
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... OKI Semiconductor (4) G.711 (u-law/A-law) 10ms mode: 2-channel processing in the midle of operation Figure 25 G.711 (μ-law/A-law Mode: Control Timing of 2-Channel Processing in the Middle of Operation FEDL7224-001FULL-01 ML7224-001TC 57/225 ...
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... OKI Semiconductor Operational Description 1) single-channel operation in progress Indicates a state in which only CH0 transmit data and receive data are being exchanged. 2) 2-channel operation activated To also activate CH1 from the single-channel operation state at CH0, set SC_CH1EN=1 (and SC_CH0EN=1). Encoder: Starts encoding CH0 and CH1 signals a maximum of 1 frame after SC_CH1EN is set to “1”. ...
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... OKI Semiconductor The following describes the operation when receive data is written in the order of CH0 to CH1. Write CH0 receive data (80 bytes) by the first receive data write request (FR1 = 1&RXREQ_First = 1). Also, before starting to write CH0 receive data, by setting the receive data write channel notification register (RXFLAG) to “ ...
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... OKI Semiconductor PCM Interface (1) Overview The PCM interface of this LSI consists of the following two interfaces, and SYNC and BCLK are common in each interface. • I/O interface (PCMO_a, PCMI_a) for CH0a/CH1a PCM data transmission/reception • I/O interface (PCMO_b, PCMI_b) for CH0b/CH1b PCM data transmission/reception (2) PCM Time Slot Configuration The bit width of one time slot of a PCM interface is fixed to 16 bits ...
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... OKI Semiconductor (3) Input Time Slot Selection Method • PCM Signal Input Pin for CH0a/CH1a (PCMI_a) The PCM data to be input from PCMI_a can be used to capture a maximum of four time slots with the four buffers (16-bit width) PCMIa input buffer 0 (ITS0a), PCMIa input buffer 1 (ITS1a), PCMIa input buffer 2 (ITS2a) and PCMIa input buffer 3 (ITS3a) ...
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... OKI Semiconductor Note: Using a PCM interface as a speech codec interface is not currently supported; therefore, ITS2a, ITS3a, ITS2b and ITS3b cannot be used necessary to use a PCM interface as a speech codec interface, contact our sales personnel. (4) Output Time Slot Selection Method • PCM Signal Output Pin for CH0a/CH1a (PCMO_a) The PCM data to be output from PCMO_a can be output two time slots with the two buffers (16-bit width) PCMOa ouptut buffer 0 (OTS0a) and PCMOa output buffer 1 (OTS1a) ...
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... OKI Semiconductor • PCM Signal Output Pin for CH0b/CH1b (PCMO_b) The PCM data to be output from PCMO_b can be output two time slots with the two buffers (16-bit width) PCMOb ouptut buffer 0 (OTS0b) and PCMOb output buffer 1 (OTS1b). These two buffers are assigned to output the PCM signals described below. (See also the Block Diagram of this LSI.) − ...
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... OKI Semiconductor Serial Control Interface (1) Overview This LSI has two systems of serial control interfaces. One serial control interface can control read and write operations to the control registers on the DSP_A side, and the other can control read and write opeations to the control registers on the DSP_B side. ...
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... OKI Semiconductor List of Control Registers (DSP_A Side) This LSI has CR0a–CR47a as control registers that perform various control and status notification on the DSP_A side, GPCR0a–GPCR8a as general-purpose input/output port control registers, and DLCR0a–DLCR5a as control registers for downloading DSP firmware. Control Register Map (DSP_A Side) [page ...
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... OKI Semiconductor Control Register Map (DSP_A Side) [page Address Reg Name A7a-A0a CR11a 0Bh ⎯ ⎯ CR12a 0Ch $ $ FD_ BW_ CR13a 0Dh SEL_a SEL_a I/ I/ PCM_ PCM_ SEL1_a SEL0_a CR14a 0Eh I/ I/ CR15a 0Fh 10h CR16a TONE_ ...
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... OKI Semiconductor Control Register Map (DSP_A Side) [page Address Reg Name A7a-A0a B7 B6 SC_CH SC_CH CR24a 18h 0EN_a 1EN_a I/E I/E TONE_ TONE_ RXDET TXDET CR25a 19h 0EN_a 0EN_a I/E I/E TONE_ TONE_ RXDET TXDET CR26a 1Ah 1EN_a 1EN_a I/E I/E DPGEN # CR27a 1Bh 0_EN_a ⎯ ...
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... OKI Semiconductor Control Register Map (DSP_A Side) [page Address Reg Name A7a-A0a B7 B6 ITS2_ # CR36a 24h SEL_a ⎯ I/E ITS3_ # CR37a 25h SEL_a ⎯ I/E OTS1_ # CR38a 26h SEL_a ⎯ I/E CR39a 27h CR41a 29h FGEN0 FGEN0 CR42a 2Ah _D7_a _D6_a ...
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... OKI Semiconductor Control Register Map (DSP_A Side) [page Address Reg Name A7a-A0a 40h # # CR0a (S:00h) ⎯ ⎯ GP 41h # # CR1a (S:01h) ⎯ ⎯ GP 42h # # CR2a (S:02h) ⎯ ⎯ GP 43h # # CR3a (S:03h) ⎯ ⎯ GP 44h # # CR4a (S:04h) ⎯ ⎯ GP 45h ...
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... OKI Semiconductor Control Register Map ( DSP_A Side) [page Address Reg Name A7a-A0a 90h # # CR0a (S:10h) ⎯ ⎯ DLa_ DLa_ DL 91h A7 A6 CR1a (S:11h DLa_ DLa_ DL 92h A15 A14 CR2a (S:12h DLa_ DLa_ DL 93h BUF7 BUF6 CR3a ...
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... OKI Semiconductor List of Control Registers (DSP_B Side) This LSI has CR0b–CR47b as control registers that perform various control and status notification on the DSP_B side, GPCR0b–GPCR8b as general-purpose input/output port control registers, and DLCR0b–DLCR5ba as control registers for downloading DSP firmware. Control Register Map (DSP_B Side) [page ...
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... OKI Semiconductor Control Register Map (DSP_B Side) [page Address Reg Name A7b-A0b CR11b 0Bh ⎯ ⎯ CR12b 0Ch $ $ FD_ BW_ CR13b 0Dh SEL_b SEL_b I/ I/ PCM_ PCM_ CR14b 0Eh SEL1_b SEL0_b I/ I/ 0Fh CR15b 10h CR16b TONE_ ...
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... OKI Semiconductor Control Register Map (DSP_B Side) [page Address Reg Nbme A7b-A0b B7 B6 SC_CH SC_CH CR24b 18h 0EN_b 1EN_b I/E I/E TONE_ TONE_ RXDET TXDET CR25b 19h 0EN_b 0EN_b I/E I/E TONE_ TONE_ RXDET TXDET CR26b 1Ah 1EN_b 1EN_b I/E I/E DPGEN # CR27b 1Bh 0_EN_b ⎯ ...
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... OKI Semiconductor Control Register Map (DSP_B Side) [page Address Reg Nbme A7b-A0b B7 B6 ITS2_ # CR36b 24h SEL_b ⎯ I/E ITS3_ # CR37b 25h SEL_b ⎯ I/E OTS1_ # CR38b 26h SEL_b ⎯ I/E CR39b 27h $ $ to to CR41b 29h FGEN0 FGEN0 CR42b 2Ah _D7_b _D6_b ...
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... OKI Semiconductor Control Register Map (DSP_B Side) [page Address Reg Nbme A7b-A0b 40h # # CR0b (S:00h) ⎯ ⎯ GP 41h # # CR1b (S:01h) ⎯ ⎯ GP 42h # # CR2b (S:02h) ⎯ ⎯ GP 43h # # CR3b (S:03h) ⎯ ⎯ GP 44h # # CR4b (S:04h) ⎯ ⎯ GP 45h ...
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... OKI Semiconductor Control Register Map (DSP_B) [page Address Reg Name A7b-A0b 90h # # CR0b (S:10h) ⎯ ⎯ DLb_ DLb_ DL 91h A7 A6 CR1b (S:11h DLb_ DLb_ DL 92h A15 A14 CR2b (S:12h DLb_ DLb_ DL 93h BUF7 BUF6 CR3b (S:13h) ...
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... OKI Semiconductor [Notation] Bit symbols Reserved bit. Do not change the initial value (“0”). $ : Access-prohibited bit. Do not perfome any read or write operation to this bit. Mode where setting can be changed: I/E : Can be changed either in the initial mode or during operation Can be changed only in the initial mode. ...
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... OKI Semiconductor (0) CR0 B7 B6 DSP_ AFE1_ CR0 RESET PDN Mode where setting can be / changed (*1) Initial value automatically set to “1” by the cancellation of hardware power down (PDNB = 0→1). Write “0” after *1: the DSP firmware has been written. ...
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... OKI Semiconductor B0: Operation start control register 0: Operation hold 1: Operation start The initial mode is entered when download of the DSP firmware is completed normally. In the initial mode, it becomes possible to modify the contents of the control registers and the internal data memory. Read out the initial mode display register (READY) repeatedly and start modifying the contents of the control registers and the internal data memory after detecting a “ ...
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... OKI Semiconductor (1) CR1 B7 B6 CR1 XDMWR XDMRD Mode where setting can be I/E I/E changed Initial value 0 0 B7: Internal data memory 1-word write control register 0: Write stopped 1: Executes 1-word write This register is used to write 1 words of data into the distributed address area in the internal data memory. ...
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... OKI Semiconductor (2) CR2 B7 B6 TGEN0 TGEN0 CR2 _TX _RX Mode where setting can be changed Initial value 0 0 B7: TGEN0 TX section output control register 0: Stops output. 1: Outputs tone at the TX section. B6: TGEN0 RX section output control register 0: Stops output. 1: Outputs tone at the RX section. B5: Register for controlling addition or multiplication of TONE A/B 0: Addition (The TONE A and TONE B outputs are added ...
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... OKI Semiconductor (3) CR3 B7 B6 TGEN1 TGEN1 CR3 _TX _RX Mode where setting can be changed Initial value 0 0 B7: TGEN1 TX section output control register 0: Stops output. 1: Outputs tone at the TX section. B6: TGEN1 RX section output control register 0: Stops output. 1: Outputs tone at the RX section. B5: Register for controlling addition or multiplication of TONE C/D 0: Addition (The TONE C and TONE D outputs are added ...
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... OKI Semiconductor Figure 28 shows block diagrams of the tone generation section (TGEN0 and TGEN1). There is no differene in the tone generation method of TGEN0 and TGEN1. Figure 29 illustrates the tone output control method, and Figures 30 and 31 show the tone output control parameters, using TGEN0 as an example. ...
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... OKI Semiconductor Single tone output method TONE A, B frequency setting TONE A/B/TOTAL gain setting M0/M1output duration setting (Common to TONE A & TONE B) FADE control setting (Common to TONE A & TONE B) "0"(FADE control stopped ) FADE IN STEP value setting (Common to TONE A/B) FADE OUT STEP value setting ...
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... OKI Semiconductor FREQ Single tone GAIN output FREQ FREQ Continuous GAIN tone output Figure 30 Tone Output Control Parameter (when TONE_GEN0 / TGEN0_FADE_CONT are set OFF) TIM_M0 TIM_M1 TIM_M0 TIM_M1 OFF TIM_M0 TIM_M1 M0 OFF M1 ON FREQ TIM_M0 TIM_M1 TIM_M0 M0 OFF ...
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... OKI Semiconductor Single tone GAIN output F-i F-i Continuous GAIN tone output GAIN GAIN_B GAIN_A F-i Figure 31 Tone Output Control Parameters (when TIM_M0 TIM_M1 Note: "F-i" and "F-o" idicate time taken for fade-in and fade-out , respectively determined by the parameters described later. ...
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... OKI Semiconductor (4) CR4 B7 B6 MGEN_ MGEN_ CR4 TCEN TBEN Mode where setting can changed Initial value TRACKC output contrl register 0 : Stop 1 : Output B6 : TRACKB output contrl register 0 : Stop 1 : Output B5 : TRACKA output contrl register 0 : Stop 1 : Output B4–B1: Reserved bits. Do not change the initial values. ...
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... OKI Semiconductor (5) CR5 B7 B6 DL_ CR5 READY ST2 Mode where ⎯ ⎯ setting can be changed Initial value 0 0 B7: Initial mode indication register 0: Other than the initial mode 1: Initialization in progress Once the downloading of the DSP firmware is completed normally, the mode enters the initial mode. This bit will be set to “ ...
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... OKI Semiconductor (6) CR6 B7 B6 A15 A14 CR6 /D15 /D14 Mode where setting can be changed (*1) (*1) Initial value 0 0 B7–B0 : Registers for setting the high-order address/high-order data of the internal data memory. For details on the method of writing, see the section on the method of accessing and controlling the internal data memory ...
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... OKI Semiconductor (9) CR9 B7 B6 CR9 D7 D6 Mode where setting can be changed (*1) (*1) Initial value 0 0 B7–B0 : Registers for setting the low-order data of the internal data memory. For details on the method of writing and reading, see the section on the method of accessing and controlling the internal data memory ...
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... OKI Semiconductor (11) CR11 B7 B6 CR11 # # Mode where ⎯ ⎯ setting can be changed Initial value Reserved bits. Do not change the initial values PCM input buffer 3 enable control register 0 : Stop 1 : Activate By setting this bit to “1”, the PCM data at the time slot position set by the PCM input buffer 3 time slot selection register (PCM_ITS3[3:0]) is captured. The capturing of PCM data will start from the next frame in which the setting of this bit to “ ...
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... OKI Semiconductor B2 : PCM input buffer 1 enable control register 0 :Stop 1 : Activate By setting this bit to “1”, the PCM data at the time slot position set by the PCM input buffer 1 time slot selection register (PCM_ITS1[3:0]) is captured. The capturing of PCM data will start from the next frame in which the setting of this bit to “ ...
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... OKI Semiconductor (12) CR12 B7 B6 CR12 $ $ Mode where ⎯ ⎯ setting can be changed ⎯ ⎯ Initial value B7–B0 : Reserved bits. Access prohibited. (13) CR13 B7 B6 FD_ BW_ CR13 SEL SEL Mode where setting can changed Initial value FRAME/DMA selection register 0 : FRAME access 1 : DMA slave interface access Select the method of accessing the transmit buffers and receive buffers ...
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... OKI Semiconductor B2 Receiving side speech codec selection register ( Setting not allowed ( G.711(μ-law Setting not allowed ( G.711(A-law) Note: Using the initial value of this register is not allowed; therefore, be sure to set either (0,1) or (1,1) while in the initial mode. ...
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... OKI Semiconductor (14) CR14 B7 B6 PCM_ PCM_ CR14 SEL1 SEL0 Mode where setting can changed Initial value PCM interface coding format selection register These bits select the PCM interface coding format Setting not allowed ( G.711 (μ-law Setting not allowed ( ...
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... OKI Semiconductor (17) CR17 B7 B6 TONE_R TONE_T CR17 XDET0 XDET0 Mode where ⎯ ⎯ setting can be changed Initial value TONE_RXDET0 detection status register “1” is set in a segment where tone is detected by TONE_RXDET0. “0” is set for any other segments. 0: Not detected ...
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... OKI Semiconductor (18) CR18 B7 B6 TONE_R TONE_T CR18 XDET1 XDET1 Mode where ⎯ ⎯ setting can be changed Initial value TONE_RXDET1 detection status register “1” is set in a segment where tone is detected by TONE_RXDET1. “0” is set for any other segment. 0: Not detected ...
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... OKI Semiconductor DTMF_3 DTMF_2 Table 4 DTMF Detection Codes Low group DTMF_1 DTMF_0 [Hz 697 0 1 770 1 0 852 1 1 941 0 0 697 0 1 770 1 0 852 ...
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... OKI Semiconductor (19) CR19 B7 B6 ANSP DSP CR19 M_TXD _ERR ET0 Mode where ⎯ ⎯ setting can be changed Initial value 0 0 B7: DSP status register 0: Normal operation state 1: Abnormal operation state This LSI has a built-in watchdog timer, and when the program of the DSP section goes into uncontrollable execution state due to external disturbances around this LSI or due to power supply abnormalities, etc., the DSP status register (DSP_ERR) will be set to “ ...
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... OKI Semiconductor (20) CR20 B7 B6 ANSP CR20 # M_TXD ET1 Mode where ⎯ ⎯ setting can be changed Initial value Reserved bits. Do not change the initial values TD_TXDET1⎯2100 Hz phase inversion detection status register 0: Not detected 1: Detected B5 : TD_TXDET1⎯2100 Hz single-tone detection status register ...
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... OKI Semiconductor (21) CR21 B7 B6 TX_SC TX_BT CR21 FLAG FLAG Mode where ⎯ ⎯ setting can be changed Initial value Transmitting side speech codec operation mode notification flag 0 : Other than G.711 (μ-law / A-law G.711 (μ-law / A-law Transmitting side buffering time operation mode notification flag ...
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... OKI Semiconductor B0 : CH0 transmission request notification register CH0 transmission request generated 1 : CH0 transmission request generated This register is set to “1” if the transmit buffer storing CH0 transmit data becomes full, and set to “0” if the reading of data in the transmit buffer is complete or the specified time is exceeded. ...
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... OKI Semiconductor (22) CR22 B7 B6 RX_SC RX_BT CR22 FLAG FLAG Mode where ⎯ ⎯ setting can be changed Initial value Receiving side speech codec operation mode notification flag 0 : Other than G.711 (μ-law / A-law G.711 (μ-law / A-law Receiving side buffering time operation mode notification flag ...
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... OKI Semiconductor ♦ Prohibited Item 1: Do not write the receive data of the same channel in succession within one frame. If the receive data of the same channel is written in succession within one frame, RXBW_ERR is set to “1”. In this case, the data written by the first reception request (FR1=1 & RXREQ_First = 1) will be decoded; however, the data written by the second reception request (FR1=1 & ...
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... OKI Semiconductor (23) CR23 B7 B6 CR23 $ $ Mode where ⎯ ⎯ setting can be changed ⎯ ⎯ Initial value B7–B0 : Reserved bits. Access prohibited. (24) CR24 B7 B6 SC_CH SC_CH CR24 0EN 1EN Mode where setting can be I/E I/E changed Initial value Speech codec-CH0 control register 0 : Stops speech codec-CH0 ...
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... OKI Semiconductor B4 : G.711 PLC funtion enable control register Enable the G.711 PLC function by setting this bit to “1” Disabled 1 : Enabled Note: When setting G711_PLCEN to “1”, be sure when a speech codec stop state Speech codec interface selection register 0 : FIFO interface 1 : PCM interface Note: Do not change the initial value (“ ...
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... OKI Semiconductor (25) CR25 B7 B6 TONE_ TONE_ CR25 RXDET TXDET 0EN 0EN Mode where setting can be I/E I/E changed Initial value TONE_RXDET0 enable control register 0 : Stop 1 : Operate Setting this bit to “1” makes TONE_RXDET0 start operating TONE_TXDET0 enable control register 0 : Stop 1 : Operate Setting this bit to “1” makes TONE_TXDET0 start operating. ...
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... OKI Semiconductor B0 : Reserved bit. Do not change the initial values. Note: If either TD_RXDET0 or TD_TXDET0 is activated, using TONE_RXDET0 is not allowed, nor is TONE_TXDET0. FEDL7224-001FULL-01 ML7224-001TC 108/225 ...
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... OKI Semiconductor (26) CR26 B7 B6 TONE_ TONE_ CR26 RXDET TXDET 1EN 1EN Mode where setting can be I/E I/E changed Initial value TONE_RXDET1 enable control register 0 : Stop 1 : Operate Setting this bit to “1” makes TONE_RXDET1 start operating TONE_TXDET1 enable control register 0 : Stop 1 : Operate Setting this bit to “1” makes TONE_TXDET1 start operating. ...
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... OKI Semiconductor (27) CR27 B7 B6 DPGEN CR27 # 0_EN Mode where ⎯ setting can be I/E changed Initial value Reserved bits. Do not change the initial values DPGEN0 transmission control register 0 : Stops transmission 1 : Output operation B5 : DPGEN0 output polarity control register 0 : Positive logic (Low: Break interval; High: Make interval Negative logic (Low:Make interval ...
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... OKI Semiconductor (28) CR28 B7 B6 DPGEN CR28 # 1_EN Mode where ⎯ setting can be I/E changed Initial value Reserved bits. Do not change the initial values DPGEN1 output control register 0 : Stops output 1 : Output operation B5 : DPGEN1 output polarity control register 0 : Positive logic (Low: Break interval; High: Make interval Negative logic (Low:Make interval ...
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... OKI Semiconductor (29) CR29 B7 B6 CR29 # # Mode where ⎯ ⎯ setting can be changed Initial value 0 0 B7–B1 : Reserved bits. Do not change the initial values FGEN0 output data setting completion flag After writing data to the FGEN0 output data setting register (FGEN0_D[7:0]), set this bit to “1”. Once the loading of data into the internal buffer of the FSK signal generation section is complete, this bit is automatically cleared to “ ...
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... OKI Semiconductor (31) CR31 B7 B6 DPDET DPDET CR31 0_D7 0_D6 Mode where setting can be changed Initial value 0 0 B7–B0 : DPDET0 detection dial pulse count display register Displays the number of detection dial pulses of DPDET0. Note: Read the DPDET0 detection dial pulse count display register (DPDET0-D[7:0]) at the timing when the value of the DPDET0 detection status register (DP0_DET) chagnes from “ ...
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... OKI Semiconductor (33) CR33 B7 B6 ITS0_ CR33 # SEL Mode where ⎯ setting can be I/E changed Initial value PCM input buffer 0 high order/low order selection register 0 : Selects low-order 8 bits 1 : Selects high-order 8 bits B6–B4 : Reserved bits. Do not change the initial values. B3–B0 : PCM input buffer 0 time slot selection register Set the number of the time slot into which PCM data will be loaded according to the selection chart shown in Table 5 ...
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... OKI Semiconductor (34) CR34 B7 B6 ITS1_ CR34 # SEL Mode where ⎯ setting can be I/E changed Initial value PCM input buffer 1 high order/low order selection register 0 : Selects low-order 8 bits 1 : Selects high-order 8 bits B6–B4 : Reserved bits. Do not change the initial values. B3–B0 : PCM input buffer 1 time slot selection register Set the number of the time slot to which PCM data will be loaded according to the selection chart shown in Table 6 ...
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... OKI Semiconductor (35) CR35 B7 B6 OTS0_ CR35 # SEL Mode where ⎯ setting can be I/E changed Initial value PCM output buffer 0 high order/low order selection register 0 : Selects low-order 8 bits 1 : Selects high-order 8 bits B6–B4 : Reserved bits. Do not change the initial values. B3–B0 : PCM output buffer 0 time slot selection register Set the number of the time slot at which PCM data will be output according to the selection chart shown in Table 7 ...
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... OKI Semiconductor (36) CR36 B7 B6 ITS2_ CR36 # SEL Mode where ⎯ setting can be I/E changed Initial value PCM input buffer 2 high order/low order selection register 0 : Selects low-order 8 bits 1 : Selects high-order 8 bits B6–B4 : Reserved bits. Do not change the initial values. B3–B0 : PCM input buffer 2 time slot selection register Set the number of the time slot to which PCM data will be loaded according to the selection chart shown in Table 8 ...
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... OKI Semiconductor (37) CR37 B7 B6 ITS3_ CR37 # SEL Mode where ⎯ setting can be I/E changed Initial value PCM input buffer 3 high order/low order selection register 0 : Selects low-order 8 bits 1 : Selects high-order 8 bits B6–B4 : Reserved bits. Do not change the initial values. B3–B0 : PCM input buffer 3 time slot selection register Set the number of the time slot to which PCM data will be loaded according to the selection chart shown in Table 9 ...
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... OKI Semiconductor (38) CR38 B7 B6 OTS1_ CR38 # SEL Mode where ⎯ setting can be I/E changed Initial value PCM output buffer 1 high order/low order selection register 0 : Selects low-order 8 bits 1 : Selects high-order 8 bits B6–B4 : Reserved bits. Do not change the initial values. B3–B0 : PCM output buffer 1 time slot selection register Set the number of the time slot at which PCM data will be output according to the selection chart shown in Table 10 ...
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... OKI Semiconductor (39) CR39 B7 B6 CR39 $ $ Mode where ⎯ ⎯ setting can be changed ⎯ ⎯ Initial value B7–B0 : Reserved bits. Access prohibited. (40) CR40 B7 B6 CR40 $ $ Mode where ⎯ ⎯ setting can be changed ⎯ ⎯ Initial value B7–B0 : Reserved bits. Access prohibited. (41) CR41 ...
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... OKI Semiconductor (42) CR42 B7 B6 FGEN0 FGEN0 CR42 _D7 _D6 Mode where setting can be changed Initial value 0 0 B7–B0 : FGEN0 output data setting register For more information, see the description of the FSK generator 0 (FSKGEN0) in the section of “INTERNAL MEMORY ACCESS AND VARIOUS CONTROL METHODS” described later. ...
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... OKI Semiconductor (44) CR44 B7 B6 T1_ T1_ CR44 TXON RXON Mode where setting can be I/E I/E changed Initial value T1_TXON switch control register connect 1 : Connect B6 : T1_RXON switch control register connect 1 : Connect B5 : R1_TXON switch control register connect 1 : Connect B4 : R1_RXON switch control register ...
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... OKI Semiconductor (45) CR45 B7 B6 CR45 # # Mode where ⎯ ⎯ setting can be changed Initial value Reserved bits. Do not change the initial values Timer control register 0 : Stops counting Starts counting Reserved bits. Do not change the initial values DPDET1 polarity control register Controls the polarity to be input from the GPIOB[1] pin ...
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... OKI Semiconductor (46) CR46 B7 B6 CR46 $ $ Mode where ⎯ ⎯ setting can be changed ⎯ ⎯ Initial value B7–B0 : Reserved bits. Access prohibited. (47) CR47 B7 B6 CR47 $ $ Mode where ⎯ ⎯ setting can be changed ⎯ ⎯ Initial value B7–B0 : Reserved bits. Access prohibited ...
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... OKI Semiconductor (48) GPCR0 B7 B6 GPCR0 # # Mode where ⎯ ⎯ setting can be changed Initial value 0 0 With this register (GPMA[1:0]), the direction (input or output) of general-purpose input/output port A[1:0] (GPIOA[1:0]) can be set for each bit. B7–B2 : Reserved bits. Do not change the initial values GPIOA[1] input/output setting register ...
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... OKI Semiconductor (49) GPCR1 B7 B6 GPCR1 # # Mode where ⎯ ⎯ setting can be changed Initial value 0 0 *1: Depends on the pin status. This register (GPDA[1:0]) stores the input/output data of general-purpose input/output port A[1:0] (GPIOA[1:0]). When it is set as a general-purpose output port value is written to any bit of this register, the written value is output from the corresponding pin ...
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... OKI Semiconductor (50) GPCR2 B7 B6 GPCR2 # # Mode where ⎯ ⎯ setting can be changed Initial value 0 0 With this register (GPFA[1:0]), the primary/secondary function of general-purpose input/output port A[1:0] (GPIOA[1:0]) can be selected. B7–B2 : Reserved bits. Do not change the initial values GPIOA[1] primary function/secondary function selection register ...
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... OKI Semiconductor (51) GPCR3 B7 B6 GPCR3 # # Mode where ⎯ ⎯ setting can be changed Initial value 0 0 With this register (GPMB[3:0]), the direction (input or output) of general-purpose input/output port B[3:0] (GPIOB[3:0]) can be set for each bit. B7–B4 : Reserved bits. Do not change the initial values GPIOB[3] input/output setting register ...
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... OKI Semiconductor (52) GPCR4 B7 B6 GPCR4 # # Mode where ⎯ ⎯ setting can be changed Initial value 0 0 *1: Depends on the pin status. This register (GPDB[3:0]) stores the input/output data of general-purpose input/output port B[3:0] (GPIOB[3:0]). When it is set as a general-purpose output port value is written to any bit of this register, the written value is output from the corresponding pin ...
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... OKI Semiconductor (53) GPCR5 B7 B6 GPCR5a $ $ Mode where ⎯ ⎯ setting can be changed Initial value 0 0 B7–B0 : Reserved bits. Access prohibited. (54) GPCR6 B7 B6 GPCR6 GPMC[7] GPMC[6] GPMC[5] GPMC[4] GPMC[3] GPMC[2] GPMC[1] GPMC[0] Mode where setting can be I/E I/E changed Initial value 0 0 With this register (GPMC[7:0]), the direction (input or output) of general-purpose input/output port C[7:0] (GPIOC[7:0]) can be set for each bit ...
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... OKI Semiconductor (55) GPCR7 B7 B6 GPCR7 GPDC[7] GPDC[6] GPDC[5] GPDC[4] GPDC[3] GPDC[2] GPDC[1] GPDC[0] Mode where setting can be I/E I/E changed (*1) (*1) Initial value *1: Depends on the pin status. This register (GPDC[7:0]) stores the input/output data of general-purpose input/output port C[7:0] (GPIOC[7:0]). When it is set as a general-purpose output port value is written to any bit of this register, the written value is output from the corresponding pin ...
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... OKI Semiconductor B2 : Data register for GPIOC[2] GPMB[2] 0: Input 1: Output B1 : Data register for GPIOC[1] GPMB[1] 0: Input 1: Output B0 : Data register for GPIOC[0] GPMB[0] 0: Input 1: Output (56) CRCR8 B7 B6 GPCR8 $ $ Mode where ⎯ ⎯ setting can be changed Initial value 1 1 B7–B0 : Reserved bits. Access prohibited. ...
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... OKI Semiconductor (57)DLCR0 B7 B6 DLCR0 # # Mode where ⎯ ⎯ setting can be changed Initial value 0 0 B7–B2 : Reserved bits. Do not change the initial values Download circuit access control register 0 : PRAM access mode 1 : DRAM access mode B0 : Download circuit activation control register 0 : Stop 1 : Activate ...
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... OKI Semiconductor (60) DLCR3 B7 B6 DL_ DL_ DLCR3 BUF7 BUF6 Mode where setting can changed (*1) (*1) Initial value *1: The initial value of this register is undefined. B7–B0 : Download data buffer register 0 When writing data to PRAM/DRAM, write data (D7-D0) via this register. (61) DLCR4 B7 B6 DL_ ...
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... OKI Semiconductor INTERNAL MEMORY ACCESS AND VARIOUS CONTROL METHODS Various controls can be performed by accessing the internal data memories of this LSI. This LSI has two built-in DSPs (DSP_A and DSP_B), each of which is embedded with separate internal data memories. The 8-bit registers CR6a–CR9a, which are mapped inside the control registers on the DSP_A side, are assigned to the following for the purpose of accessing the internal data memory on the DSP_A side ...
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... OKI Semiconductor Write Method (1 Word) By setting the internal data memory 1-word write control register (XDMWR) to “1” after setting an internal data memory address and write data in CR6–CR9, the writing of internal data memory for one word will be completed. XDMWR will automaticlly be cleared to “0” upon completion of a write operation. Figure 34 shows the method of writing one word to an internal data memory ...
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... OKI Semiconductor Write Method (Multiple Words) When writing to contiguous address spaces in an internal data memory, multiple words (2N words) can be written consecutively without setting addresses individually, as described below. 1) Setting the Start Address Set the starting address according to the write method (1 word) shown in Figure 34. ...
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... OKI Semiconductor Start of writing multiple words (2N words) NO CR1 = 00h? CR6 (Internal memory ; higher address ) CR7 (Internal memory ; lower address ) CR8 (Internal memory ; higher data ) CR9 (Internal memory ; lower data) Internal memory is updated . XDMWR is cleared automatically. NO CR1 = 00h? CR6 (Internal memory ; higher address ) CR7 (Internal memory ...
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... OKI Semiconductor Read Method After setting the internal data memory address in CR6 and CR7, one word of data from the internal data memory is stored in CR8 and CR9 setting the internal data memory read control register (XDMRD) to “1”. After reading the data, XDMRD will be cleared to “0” automatically. The method of reading the internal data memory is shown in Figure 36 ...
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... OKI Semiconductor In tables that follow, note the following terms/symbols and their meaning: Initial mode: Indicates the state after completion of downloading of the DSP firmware, and in which the initial values of control registers and internal data memories can be changed. During idle state: Indicates the state in which the function given in the function name column is being stopped ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 2 of 12) Function Internal data memory name / related name control register name Tone TGEN0 transmission control register genera- tion 0 TONE A frequency control (TGEN0_FREQ_A) TGEN0 TONE B frequency control (TGEN0_FREQ_B) TONE A gain control (TGEN0_GAIN_A) ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 3 of 12) Function Internal data memory name / related name control register name Tone TGEN1 transmission control register genera- tion 1 TONE C frequency control (TGEN1_FREQ_C) TGEN1 TONE D frequency control (TGEN1_FREQ_D) TONE C gain control (TGEN1_GAIN_C) ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 4 of 12) Function Internal data memory name / related name control register name FSK0 FGEN0 enable control register genera- (FGEN0_EN) tor FGEN0 output data setup completion flag (FGEN0_FLAG) FSK GEN0 FGEN0 output data setup register ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 5 of 12) Function Internal data memory name / related name control register name TONE TONE_RXDET0 enable control detector register (TONE_RXDET0EN) RX0 TONE_RXDET0 detection status register TONE_ RX (TONE_RXDET0) DET0 Internal data memory for ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 6 of 12) Function Internal data memory name / related name control register name TONE TONE_RXDET1 enable control detector register (TONE_RXDET1EN) RX1 TONE_RXDET1 detection status register (TONE_RXDET1) TONE_ RX Internal data memory for ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 7 of 12) Function Internal data memory name / related name control register name Tone TD_RXDET0 enable control register disabler (TD_RXDET0_EN) TD0 TD_RXDET0 2100 Hz single-tone detection status register (ANS_RXDET0) TD_RXDET0 2100 Hz phase inversion ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 8 of 12) Function Internal data memory name / related name control register name Tone TD_RXDET1 enable control register disabler (TD_RXDET1_EN) TD1 TD_RXDET1 2100 Hz single-tone detection status register (ANS_RXDET1) TD_RXDET1 2100 Hz phase inversion ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 9 of 12) Function Internal data memory name / related name control register name DTMF DTMF0 enable control register detector (DTMF0_EN) DTMF0 detection code indication DTMF register (DTMF0_C[3:0]) DET0 DTMF0 detection status register ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 10 of 12) Function Internal data memory name / related name control register name DP DPDET0 activation control register detector (DPDET0_EN) DPDET0 detection status register DP (DP0_DET) DET0 DPDET0 polarity control register (DPDET0_POL) DPDET0 dial pulse count indication ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 11 of 12) Function Internal data memory name / related name control register name DP DPGEN0 transmit control register trans- (DPGEN0_EN) mitter DPGEN0 dial pulse count setup register (DPGEN0_D[3:0]) DP GEN0 DPGEN0 speed control register ...
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... OKI Semiconductor Table 11 List of Internal Data Memories and Related Control Registers (Page 12 of 12) Function Internal data memory name / name related control register name Melody MGEN high-speed read mode genera- control register (MGEN_FREN) tor MGEN MGEN high-speed read mode notification flag (MGEN_FRFLAG) ...
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... OKI Semiconductor Gain Control A. Gain related to the transmit path A-1 : Internal data memory for adjusting CH0 transmit gain 0 (TXGAIN0_CH0) Initial value : 0080h (0.0 dB) When changing the gain value, compute it using the following equation: Equation: 0080h × GAIN Example: Making the gain +6 dB (× 2): 0080h × ...
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... OKI Semiconductor B. Gain related to the receive path B-1 : Internal data memory for adjusting CH0 receive gain 0 (RXGAIN0_CH0) Initial value : 0080h (0.0 dB) When changing the gain value, compute it using the following equation: Equation: 0080h × GAIN Example: Making the gain +6 dB (× 0080h × 0100h Upper limit : Approx ...
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... OKI Semiconductor C. Side tone gain C-1 : Internal data memory for adjusting CH0 side tone gain (STGAIN_CH0) Initial value : 0000h (MUTE) When changing the side tone gain value, compute it using the following equation: Equation: 1000h × GAIN Example: Making the gain –20 dB (× 0.1 ): 1000h × ...
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... OKI Semiconductor D. Internal Data Memory for Gain Fade Control (GAIN_FADE_CONT) The function for attenuating or amplifying to the gain after change at the specified step (gain fade-in/fade-out function) is provided for cases where the amount of gain has been changed except for the side tone gain. ...
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... OKI Semiconductor B0 : TXGAIN0_CH0_FADECONT control (Performs fade-in/out processing when changing TXGAIN0_CH0 OFF E. Internal data memory for gain fade-in step value control (GAIN_FADE_IN_ST) Initial value: 4C10h (+1.5dB) When changing the step amount X, compute it using the following equation: Equation: 10^ (X/20)*16384 Example: Making the step value +3 dB: 10^ (3/20)*16384 = 23143d = 5A67h Maximum step value: +6 ...
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... OKI Semiconductor Tone Generator 0 (TGEN0 ) This generator can generate various tones on both the transmit and receive sides of CH0. The following describes various parameters that can be set for this generator. A. Internal data memory for tone frequency control TONE A frequency control (TGEN0_FREQ_A) Initial value: 0CCDh (400 Hz) ...
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... OKI Semiconductor C. Internal data memory for tone output time control (TGEN0_TIM_M0/TGEN0_TIM_M1) TGEN0 output time control 0 (TGEN0_TIM_M0) Initial value: 0FA0h (500ms) TGEN0 output time control 1 (TGEN0_TIM_M1) Initial value: 0FA0h (500ms) Compute the value using the following equation when changing the time durations: Equation: T/0 ...
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... OKI Semiconductor F. Internal data memory for TGEN0 fade-in step value control (TGEN0_FADE_IN_ST) Initial value: 47CFh (+1.0 dB) When changing the step amount X, compute it using the following equation: Equation: 10^ (X/20)*16384 Example: Making the step value +3 dB: 10^ (3/20)*16384 = 23143d = 5A67h Maximum step value: +6.0 dB (data: 7FB2h) Minimum step value: +0 ...
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... OKI Semiconductor J. Internal data memory for TGEN0 total gain fade-in step value control (TGEN0_GAIN_TOTAL_FADE_IN_ST) Initial value: 4C10h (+1.5 dB) When changing the step amount X, compute it using the following equation: Equation: 10^ (X/20)*16384 Example: Making the step value +3 dB: 10^ (3/20)*16384 = 23143d = 5A67h Maximum step value: +6.0 dB Minimum step value: +0 ...
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... OKI Semiconductor Tone Generator 1 (TGEN1 ) This generator can generate various tones on both the transmit and receive sides of CH1. The following describes various parameters that can be set for this generator. A. Internal data memory for tone frequency control TONE C frequency control (TGEN1_FREQ_C) Initial value: 0CCDh (400 Hz) ...
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... OKI Semiconductor C. Internal data memory for tone output time control (TGEN1_TIM_M0/TGEN1_TIM_M1) TGEN1 output time control 0 (TGEN1_TIM_M0) Initial value: 0FA0h (500 ms) TGEN1 output time control 1 (TGEN1_TIM_M1) Initial value: 0FA0h (500 ms) Compute the value using the following equation when changing the time durations: Equation: T/0 ...
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... OKI Semiconductor F. Internal data memory for TGEN1 fade-in step value control (TGEN1_FADE_IN_ST) Initial value: 47CFh (+1.0 dB) When changing the step amount X, compute it using the following equation: Equation: 10^ (X/20)*16384 Example: Making the step value +3 dB: 10^ (3/20)*16384 = 23143d = 5A67h Maximum step value: +6.0 dB (data: 7FB2h) Minimum step value: +0 ...
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... OKI Semiconductor J. Internal data memory for TGEN1 total gain fade-in step value control (TGEN1_GAIN_TOTAL_FADE_IN_ST) Initial value: 4C10h (+1.5 dB) When changing the step amount X, compute it using the following equation: Equation: 10^ (X/20)*16384 Example: Making the step value +3 dB: 10^ (3/20)*16384 = 23143d = 5A67h Maximum step value: +6.0 dB Minimum step value: +0 ...
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... OKI Semiconductor FSK Generator 0 (FSKGEN0) The FSK generator 0 (FSKGEN0) can generate the FSK signal on the receive side of CH0. This generator modulates the data set in a control register with frequency modulation and outputs it to VFRO0. Table 12 shows the specifications of the FSK generator 0, and Figure 37 shows its block diagram. ...
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... OKI Semiconductor FGEN0_EN Continuous output of a mark bit (“1”) VFRO0 FGEN0_D[7:0] setting timing FGEN0_FLAG Figure 39 FSK Data Transmission and Stop Timings (When Transmitting 50 Bits) Figure 40 FSK Output Control Method Continuous 10-bit output 10-bit output output of a period period mark bit (“1”) ...
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... OKI Semiconductor A. FGEN0 enable control register (FGEN0_EN) 0: Stops FGEN0 (initial value) 1: Operates FGEN0 B. FGEN0 output data setting completion flag (FGEN0_FLAG) After writing data to the FGEN0 output data setting register (FGEN0_D[7:0]), set this bit to “1”. Once the loading of data into the internal buffer of the FSK signal generation section is complete, this bit is automatically cleared to “ ...
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... OKI Semiconductor FSK generator 1 (FSKGEN1) The FSK generator 1 (FSKGEN1) can generate the FSK signal on the receive side of CH1. This generator modulates the data set in a control register with frequency modulation and outputs it to VFRO1. Table 13 shows the specifications of the FSK generator 1, and Figure 41 shows its section diagram. ...
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... OKI Semiconductor FGEN1_EN Continuous output of a mark bit (“1”) VFRO1 FGEN1_D[7:0] setting timing FGEN1_FLAG Figure 43 FSK Data Transmission and Stop Timings (When Transmitting 50 Bits) Figure 44 FSK Output Control Method Continuous 10-bit output 10-bit output output of a period period mark bit (“1”) ...
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... OKI Semiconductor A. FGEN1 enable control register (FGEN1_EN) 0: Stops FGEN1 (initial value) 1: Operates FGEN1 B. FGEN1 output data setting completion flag (FGEN1_FLAG) After writing data to the FGEN1 output data setting register (FGEN1_D[7:0]), set this bit to “1”. Once the loading of data into the internal buffer of the FSK signal generation block is complete, this bit is automatically cleared to “ ...
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... OKI Semiconductor TONE Detector RX0 (TONE_RXDET0) The tone detector RX0 is a 400 Hz tone detector mounted on the receive side of CH0. TONE_RXDET0 consists of a main signal detection section that detects signals having the applicable frequency, a noise detection section that detects signals having other than the applicable frequency guard timer and a OFF guard timer, and detects input 400 Hz single tone signals. TONE_RXDET0 is enabled when the control register TONE_RXDET0EN is “ ...
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... OKI Semiconductor D. Internal data memory for TONE_RXDET0 noise detection level control (TONE_RXDET0_N_TH) Initial value: 1EBBh (–5.3 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X – 3.17)/20)*2/PI*32768 Example: Detect level of –5.3 dBm0 10^((–5.3 – 3.17)/20)*2/PI*32768 = 7867d = 1EBBh Upper limit: 3.17 dBm0 : – ...
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... OKI Semiconductor TONE Detector TX0 (TONE_TXDET0) The tone detector TX0 is a 400 Hz tone detector mounted on the transmit side of CH0. TONE_TXDET0 consists of a main signal detection section that detects signals having the applicable frequency, a noise detection section that detects signals having other than the applicable frequency guard timer and a OFF guard timer, and detects input 400 Hz single tone signals. TONE_TXDET0 is enabled when the control register TONE_TXDET0EN is “ ...
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... OKI Semiconductor D. Internal data memory for TONE_TXDET0 noise detection level control (TONE_TXDET0_N_TH) Initial value: 1EBBh (–5.3 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X – 3.17)/20)*2/PI*32768 Example: Detect level of –5.3 dBm0 10^((–5.3 – 3.17)/20)*2/PI*32768 = 7867d = 1EBBh Upper limit: 3.17 dBm0 : – ...
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... OKI Semiconductor TONE Detector RX1 (TONE_RXDET1) The tone detector RX1 is a 400 Hz tone detector mounted on the receive side of CH0. TONE_RXDET1 consists of a main signal detection section that detects signals having the applicable frequency, a noise detection section that detects signals having other than the applicable frequency guard timer and a OFF guard timer, and detects input 400 Hz single tone signals. TONE_RXDET1 is enabled when the control register TONE_RXDET1EN is “ ...
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... OKI Semiconductor D. Internal data memory for TONE_RXDET1 noise detection level control (TONE_RXDET1_N_TH) Initial value: 1EBBh (–5.3 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X – 3.17)/20)*2/PI*32768 Example: Detect level of –5.3 dBm0 10^((–5.3 – 3.17)/20)*2/PI*32768 = 7867d = 1EBBh Upper limit: 3.17 dBm0 : – ...
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... OKI Semiconductor TONE Detector TX1 (TONE_TXDET1) The tone detector TX1 is a 400 Hz tone detector mounted on the transmit side of CH0. TONE_TXDET1 consists of a main signal detection section that detects signals having the applicable frequency, a noise detection section that detects signals having other than the applicable frequency guard timer and a OFF guard timer, and detects input 400 Hz single tone signals. TONE_TXDET1 is enabled when the control register TONE_TXDET1EN is “ ...
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... OKI Semiconductor D. Internal data memory for TONE_TXDET1 noise detection level control (TONE_TXDET1_N_TH) Initial value: 1EBBh (–5.3 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X – 3.17)/20)*2/PI*32768 Example: Detect level of –5.3 dBm0 10^((–5.3 – 3.17)/20)*2/PI*32768 = 7867d = 1EBBh Upper limit: 3.17 dBm0 : – ...
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... OKI Semiconductor Tone Disabler 0 (TD_RXDET0/TD_TXDET0) The tone disabler 0 detects the phase inverted signal (ANSPM 2100 Hz single tone signal input to the receive and transmit sides of CH0, and also detectes the single tone signal (ANS). The tone disabler 0 can be activated individually for reception and transmission using the control registers TD_RXDET0_EN and TD_TXDET0_EN. ...
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... OKI Semiconductor A-4. : Internal data memory for TD_RXDET0 detection level control (TD_RXDET0_TH) Initial value : 241Fh (–34 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X–3.17)/20)*(2^21)/PI Example: Detection level of –34 dBm0 10^((–34–3.17)/20)*(2^21)/PI = 9247d = 241Fh Upper limit: – ...
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... OKI Semiconductor B-4. : Internal data memory for TD_TXDET0 detection level control (TD_TXDET0_TH) Initial value : 241Fh (–34 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X–3.17)/20)*(2^21)/PI Example: Detection level of –34 dBm0 10^((–34–3.17)/20)*(2^21)/PI = 9247d = 241Fh Upper limit: – ...
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... OKI Semiconductor Tone Disabler 1 (TD_RXDET1/TD_TXDET1) The tone disabler 1 detects the phase inverted signal (ANSPM 2100 Hz single tone signal input to the receive and transmit sides of CH1, and also detectes the single tone signal (ANS). The tone disabler 1 can be activated individually for reception and transmission using the control registers TD_RXDET1_EN and TD_TXDET1_EN. ...
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... OKI Semiconductor A-4. : Internal data memory for TD_RXDET1 detection level control (TD_RXDET1_TH) Initial value : 241Fh (–34 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X–3.17)/20)*(2^21)/PI Example: Detection level of –34 dBm0 10^((–34–3.17)/20)*(2^21)/PI = 9247d = 241Fh Upper limit: – ...
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... OKI Semiconductor B-4. : Internal data memory for TD_TXDET1 detection level control (TD_TXDET1_TH) Initial value : 241Fh (–34 dBm0) Compute the setting value using the following equation when changing the detection level X. Equation: 10^((X–3.17)/20)*(2^21)/PI Example: Detection level of –34 dBm0 10^((–34–3.17)/20)*(2^21)/PI = 9247d = 241Fh Upper limit: – ...
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... OKI Semiconductor DTMF Detector 0 (DTMFDET0) This detector can detect the DTMF signal on the transmit side of CH0. The DTMF detector 0 consists of a DTMF detection section that detects the DTMF signal, a noise detection section that detects signals other than the DTMF signal guard timer and a OFF guard timer. ...
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... OKI Semiconductor (Note) The level set in the data memory (DTMF0_TH) described above is used as the common detection level in the DTMF detection block and the noise detection block. E. Internal data memory for DTMF0 detection ON guard timer (DTMF0_ON_TM) Initial value : 00A0h (20 ms) Use the following equation when changing the timer value. ...
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... OKI Semiconductor DTMF Detector 1 (DTMFDET1) This detector can detect the DTMF signal on the transmit side of CH1. The DTMF detector 1 consists of a DTMF detection section that detects the DTMF signal, a noise detection section that detects signals other than the DTMF signal guard timer and a OFF guard timer. ...
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... OKI Semiconductor (Note) The level set in the data memory (DTMF1_TH) described above is used as the common detection level in the DTMF detection block and the noise detection block. E. Internal data memory for DTMF1 detection ON guard timer (DTMF1_ON_TM) Initial value : 00A0h (20 ms) Use the following equation when changing the timer value. ...
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... OKI Semiconductor Echo Canceller 0 Echo canceller echo canceller for CH0. The block diagram of echo canceller 0 is shown in Figure 53. The echo canceller 0 has a delay time and is activated by setting the echo canceller 0 control register (EC0_EN) to “1”. The operation setting of the echo canceller 0 is done mainly using internal data memories EC0_CR and EC0_GLPAD_CR ...
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... OKI Semiconductor B7: Through mode control 1: Through mode 0: Normal mode (echo cancelling operation) The data of Rin and Sin is output directly to Rout and Sout while retaining their respective echo coefficients. Further, during the through mode, the HLD, HDB, CLP, and ATTB functions are disabled. ...
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... OKI Semiconductor C. Internal data memory for EC0 GLPAD control (EC0_GLPAD_CR) Initial value: 000Fh This data memory controls the GLPAD within the echo canceller 0. Bit B15 B14 Name — — Initial value 0 0 Bit B7 B6 Name — — Initial value 0 0 B15–B4: Reserved bits. Do not change the initial values. ...
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... OKI Semiconductor E. Precautions in using the echo canceller E-1 In the echo path, make sure that the echo signal does not cause saturation, waveform distortion, etc., in the external amplifier, etc. The echo attenuation becomes poor if any saturation or waveform distortion occurs. E-2 Make the settings so that the echo return loss (E.R.L.) is attenuating. Further recommended to use the GLPAD function if the E ...
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... OKI Semiconductor Echo Canceller 1 Echo canceller echo canceller for CH1. The block diagram of echo canceller 1 is shown in Figure 54. The echo canceller 1 has a delay time and is activated by setting the echo canceller 1 control register (EC1_EN) to “1”. The operation setting of the echo canceller 1 is done mainly using internal data memories EC1_CR and EC1_GLPAD_CR ...
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... OKI Semiconductor B7: Through mode control 1: Through mode 0: Normal mode (echo cancelling operation) The data of Rin and Sin is output directly to Rout and Sout while retaining their respective echo coefficients. Further, during the through mode, the HLD, HDB, CLP, and ATTB functions are disabled. ...
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... OKI Semiconductor C. Internal data memory for EC1 GLPAD control (EC1_GLPAD_CR) Initial value: 000Fh This data memory controls the GLPAD within the echo canceller 1. Bit B15 B14 Name — — Initial value 0 0 Bit B7 B6 Name — — Initial value 0 0 B15–B4: Reserved bits. Do not change the initial values. ...
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... OKI Semiconductor E. Precautions in using the echo canceller E-1 In the echo path, make sure that the echo signal does not cause saturation, waveform distortion, etc., in the external amplifier, etc. The echo attenuation becomes poor if any saturation or waveform distortion occurs. E-2 Make the settings so that the echo return loss (E.R.L.) is attenuating. Further recommended to use the GLPAD function if the E ...
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... OKI Semiconductor Dial Pulse Detector 0 (DPDET0) The dial pulse detector 0 can detect dial pulse signals input from the general-purpose input/output port GPIOB[0]. The dial pulse detector 0 is enabled when the DPDET0 activation control register (DPDET0_EN) is “1”, the DPDET0 detection status register (DP0_DET) is set to “1” when a dial pulse signal is detected, and it is stored in the DPDET0 detection dial pulse count display register (DPDET0_D[7:0]). Read the dial pulse count detected when DP0_DET changes from “ ...
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... OKI Semiconductor C. DPDET0 polarity control register (DPDET0_POL) Controls the polarity input from the GPIOB[0] pin Does not invert polarity. (Initial value Inverts polarity. D. DPDET0 detected dial pulse count display register (DPDET0_D[7:0]) Initial value : 00h (State where no dial pulse detected) Displays the number of detected dial pulses. This register is updated when an edge is detected. ...
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... OKI Semiconductor Dial Pulse Detector 1 (DPDET1) The dial pulse detector 1 can detect dial pulse signals input from the general-purpose input/output port GPIOB[1]. The dial pulse detector 1 is enabled when the DPDET1 activation control register (DPDET1_EN) is “1”, the DPDET1 detection status register (DP1_DET) is set to “1” when a dial pulse signal is detected, and it is stored in the DPDET1 detection dial pulse count display register (DPDET1_D[7:0]). Read the dial pulse count detected when DP1_DET changes from “ ...
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... OKI Semiconductor C. DPDET1 polarity control register (DPDET1_POL) Controls the polarity input from the GPIOB[1] pin Does not invert polarity. (Initial value Inverts polarity. D. DPDET1 detected dial pulse count display register (DPDET1_D[7:0]) Initial value : 00h (State where no dial pulse detected) Displays the number of detected dial pulses. This register is updated when an edge is detected. ...