msm9225 Oki Semiconductor, msm9225 Datasheet - Page 60

• Manufacturer Part Number: msm9225
• Description: Can Controller Area Network Controller
• Manufacturer: Oki Semiconductor

(3) Data bit synchronization
(a) Hardware synchronization
(b) Bit synchronization
¡ Semiconductor
CAN bus
CAN bus
Since there is no sync signal for the receive node, synchronization is obtained from level
changes on the bus.
The transmit node transmits data is synchronization with the transmit node bit timing.
Hardware synchronizaion is the bit synchronization performed when a receive node in the bus
idle state detects a start-of-frame.
If a falling edge is detected on the bus, that bit is the sync segment and is followed by the prop
segment. In this case, syncronization is obtained without regard for SJW.
After reset and after wake up, it is necessary to obtain bit synchronization.
Therefore, hardware synchronizes to the first bus level change only.
If a level change is detected on the bus during receprion, bit synchronization is obtained.
There are two methods of synchronization.
During the bit timing interval specified by SJW, synchronization is obtained only if an edge is
detected.
The data sampling point of the receive node will move in relation to the shift in baud rate
between the transmit node and receive node.
The range of allowable "shift" is defined as "SJW". The SJW range is centered on the sync
segment and extends both before and after that segment (+/– baud rate). If an edge occurs
within the SJW range, synchronization is obtained.
If an edge occurs outside the SJW range, synchronization is not obtained.
The bit detected at the edge forces the sync segment, and is followed by the prop segment.
The bit timing is restarted.
Bit timing
Bit timing
Normal operation: falling edge of level
Low-speed operation: falling edge and rising edge of level
Previous bits
Bus idle
Sync segment Prop segment
Sync segment Prop segment
SJW
Start-of-frame
segment 1
segment 1
Later bits
Phase
Phase
segment 2
segment 2
Phase
Phase
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