msm7717 Oki Semiconductor, msm7717 Datasheet - Page 5

• Manufacturer Part Number: msm7717
• Description: Msm7717-01/02/03single Rail Codec
• Manufacturer: Oki Semiconductor

¡ Semiconductor
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to
the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted
with respect to the output of AOUT–. Since these outputs provide differential drive of an
impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being
activated during the power-saving mode, the amplifiers can output other external signals from
AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during
the power-down mode.
V
Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive
driver amplifiers are in the operating mode and the other circuits are in the non-operating mode.
DD
External Signal Input
SG
SG
Receive filter
–
+
–
+
AOUT–
AOUT+
VFRO
PWI
Analog output
Analog inverted output
R6
VI
R7
VO
ZL
ZL > 1.2 kW
R6 > 20 kW
Gain = VO/VI = R7/R6 £ 1
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