msm7719-01 Oki Semiconductor, msm7719-01 Datasheet - Page 6

• Manufacturer Part Number: msm7719-01
• Description: Echo Canceler With Adpcm Transcoder
• Manufacturer: Oki Semiconductor

MSM7719-01
¡ Semiconductor
IOSL0-1
These pins specify PCM signal I/O mode for the PCMACO, PCMACI, PCMADO, and PCMADI
pins. Since The IOSL0 and IOSL1 pins are ORed with the control register bits CR3-B6 and B5, set
these bits to logic “0” before using these pins. When this pin control is not used (i.e., in the case of
control with the control register), set these pins to logic “0”.
Refer to Figs. 1-5.
IS
Transmit ADPCM data output.
This data is serially output from MSB in synchronization with the rising edge of BCLKA and SYNCA.
This pin is in a high impedance state except during 4-bit ADPCM output. When CONTA is set to
logic “1”, this pin becomes an 8-bit output and the data that passed through the ADPCM transcoder
is output. In this case, this pin is in a high impedance state except during 8-bit output.
(This pin is also in a high imedance state during power-down or initial mode.)
Refer to Figs. 1-5.
IR
Receive ADPCM data input.
ADPCM is shifted in on the rising edge of BCLKA in synchronization with SYNCA and input
data orderly from MSB. When CONTA is set to logic “1”, this pin becomes an 8-bit input and the
data is passed through the ADPCM transcoder and processed. This pin is provided with a 500-kW
pull-up resistor.
PCMLNO
PCM receive data output of the line echo canceler.
PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and
SYNCP.
This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic
“1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as
it is. In this case, this pin is in a high impedance state except during 4-bit output.
(This pin is also in a high impedance state during power-down or initial mode.)
Refer to Figs. 1-5.
PCMLNI
PCM transmit data input of the line echo canceler.
PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM
data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”, this pin becomes
a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided
with a 500-kW pull-up resistor.
Refer to Figs. 1-5.
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