msm7652 Oki Semiconductor, msm7652 Datasheet - Page 15

• Manufacturer Part Number: msm7652
• Description: Ntsc/pal Digital Video Encoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
CLOCK TIMING2 (8bit Y/8bit CbCr input)
Input Data Timing
Input data and sync signals are fed into the encoder at the rising edge of CLKX2.
Input data is handled as valid pixel data when t
Chrominance signal of input data at this time is regarded as Cb.
Input data is recognized as valid pixel data when input signal BLANK_L is "H" in the t
When BLANK_L is "H" during the blanking period, however, input data is not output as valid
pixel data since processing to maintain blanking period is internally in-progress.
The values of t
t
In YCbCr format input mode, the values of t
or in 8 bit (YCbCr) mode.
START
are as follows.
In master mode
t
STA
Operation mode
ITU 601 NTSC
ITU 601 PAL
CLKX2
HSYNC_L
YD, CD,
OLR, OLB,
OLG,OLC
BLANK_L
– t
START
S1
= t
START
differ slightly between in master mode and in slave mode. The values of
don't care
t
t
START
Video data input timing
STA
(Ts)
250
280
t
s1
START
ACTIVE VIDEO LINE
START
t
h1
are the same, in 8 bit (Y) + 8 bit (CbCr) mode
VALID DATA
passes after the falling edge of HSYNC_L.
t
In slave mode
ACT
Operation mode
ITU 601 NTSC
ITU 601 PAL
don't care
t
STA
(Ts)
260
290
ACT
MSM7652
period.
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