ml22865 Oki Semiconductor, ml22865 Datasheet - Page 11

• Manufacturer Part Number: ml22865
• Description: Speech Synthesis Lsi With Built-in P2rom Including 2-channel Mixing Function
• Manufacturer: Oki Semiconductor

FUNCTIONAL DESCRIPTION
Synchronous Serial Command Interface
The CSB, SCK, SI, and SO pins are used to input the command data or to read the status. Driving the CSB pin
to “L” level enables the serial CPU interface.
After the CSB pin is driven to “L” level, the command data are input through the SI pin from the MSB
synchronized with the SCK clock. The command data shifts in through the SI pin at the rising or falling edge
of the SCK clock pulse. Then, a command is executed at the rising or falling edge of the eighth pulse of the
SCK clock.
As for status reading, status is output from the SO pin, synchronized with the SCK clock after the CSB pin is
driven to “L” level.
The SCK clock edge is specified by the input level of the DIPH pin.
It is possible to input command data, even if the CSB pin is fixed by “L” level. However, if unexpected pulses
caused by noise are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a failure in
normal recognition of command. Then it is recommended that the CSB pin is “L” level only for command
input.
The count of the SCK clock pulse is initialized when the CSB pin goes to “H” level.
- When the DIPH pin is “L” level, rising edge is available for input from SI pin and falling edge is available
- When the DIPH pin is “H” level, falling edge is available for input from SI pin and rising edge is available
for output from SO pin.
for output from SO pin.
• When DIPH pin is “L” level
• When DIPH pin is “H” level
Command Data Input or Status Read Timing
CSB
CSB
SCK
SCK
SO
SO
SI
SI
(
(
MSB
MSB
D7
D7
D7
D7
)
)
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
D2
D2
D2
D2
D 1
D 1
D 1
D 1
(
(
LSB
LSB
D0
D0
D0
D 0
)
)
ML2282X-XXX/ ML2286X -XXX
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