ml2240 Oki Semiconductor, ml2240 Datasheet - Page 5

• Manufacturer Part Number: ml2240
• Description: 4-channel Mixing Oki Adpcm Algorithm-based Speech Synthesis Lsi
• Manufacturer: Oki Semiconductor

OKI Semiconductor
Pin No.
45
46
47
48
50
51
53
54
56
58
59
D4/STASEL
Pin Symbol
D6/SCK
AOUTR
SERIAL
AOUTL
D5/DO
DAOR
DAOL
D7/DI
RCS
ROE
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
CPU interface data bus pin in the parallel input interface.
This pin becomes a data input pin when WR is at "L" level. It becomes
a channel status output pin when RD is at "L" level. It outputs a BUSY
signal for channel 1. For the serial input interface, it becomes a
channel status changeover pin. When D4/STASEL is at "L" level, the
D3/STA3-D0/STA0 pins output the NCR (Next Command Request)
for each channel. When the D4/STASEL is at "H" level, the
D3/STA3-D0/STA0 pins output BUSY signals for their corresponding
channels.
CPU interface data bus pin in the parallel input interface.
This pin becomes a data input pin when WR is at “L” level. It becomes
a channel status output pin when RD is at “L” level. This pin outputs 2
channels of BUSY signal.
When CS and RD are at “L” level, this D5/DO pin serially outputs the
status of each channel in synchronization with D6/SCK clock.
CPU interface data bus pin in the parallel input interface.
This pin becomes a data input pin when WR is at "L" level. It becomes
a channel status output pin when RD is at "L" level. It outputs a BUSY
signal for channel 3.
This pin becomes a serial clock input pin for the serial input interface.
When the SCK pin input is at "L" level on the falling edge of the CS pin
signal, the DI pin input signal goes into the device on at the rising edge
of the SCK clock, and the data is output from the DO pin. When the
SCK pin input is at "H" level on the falling edge of the CS pin signal,
the DI pin input signal goes into the device on the falling edge of the
SCK clock, and the data is output from the DO pin.
CPU interface data bus pin in the parallel input interface.
When WR is at "L" level, it becomes a data input pin. When RD is at
"L" level, it becomes a channel status output pin. It outputs a BUSY
signal for channel 4.
For the serial input interface, this pin becomes a serial data input pin.
Works as serial data input pin in the serial input interface.
Outputs the left 14-bit DAC analog signal.
Outputs the left 14-bit DAC analog signal via voltage follower.
Outputs the right 14-bit DAC analog signal.
Outputs the right 14-bit DAC analog signal via voltage follower.
“L” level: RA22-0, A-1, and ROE pins output the address data and the
output enable signal.
“H” level: RA22-0, A-1, and ROE pins are in high impedance.
Output enable pin for an externally connected memory.
RCS pin = “H” level: High impedance
CPU interface switching pin.
“H” level: Serial input interface, “L” level: Parallel input interface
Description
FEDL2240DIGEST-02
ML2240 Family
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