mt8885an1 Zarlink Semiconductor, mt8885an1 Datasheet - Page 13

• Manufacturer Part Number: mt8885an1
• Description: Integrated Dtmf Transceiver With Power-down And Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor

NOTE: The adaptive micro interface relies on high-to-low transition on CS to recognize the microcontroller
interface. This pin must not be tied permanently low. Only one register access is allowed on any CS assertion.
The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write
operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the
same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-
only status register indicates the current transceiver state (see Table 8).
A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 14). Refer to Tables 4-7 for bit descriptions of the two control registers.
The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when
the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a
square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external
pull-up resistor (see Figure 13).
RS0
0
0
1
1
Motorola
RSEL
R/W
C/R
b3
b3
0
1
0
1
Table 3 - Internal Register Functions
Table 4 - CRA Bit Positions
Table 5 - CRB Bit Positions
WR
Zarlink Semiconductor Inc.
0
1
0
1
Intel
S/D
IRQ
b2
b2
MT8885
RD
1
0
1
0
13
CP/DTMF
Write to Transmit
Data Register
Read from Receive
Data Register
Write to Control Register
Read from Status Register
RxEN
b1
b1
Function
ENABLE
BURST
TOUT
b0
b0
Data Sheet