mt8870dsr1-1 Zarlink Semiconductor, mt8870dsr1-1 Datasheet - Page 6

• Manufacturer Part Number: mt8870dsr1-1
• Description: Integrated Dtmf Receiver With Enhance Sensitivity
• Manufacturer: Zarlink Semiconductor

MT8870D/MT8870D-1
Data Sheet
Different steering arrangements may be used to select independently the guard times for tone present (t
) and
GTP
tone absent (t
). This may be necessary to meet system specifications which place both accept and reject limits
GTA
on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system
parameters such as talk off and noise immunity. Increasing t
improves talk-off performance since it reduces the
REC
probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively,
a relatively short t
with a long t
would be appropriate for extremely noisy environments where fast acquisition
REC
DO
time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure
5.
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby
mode. It stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing
characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1).
Differential Input Configuration
The input arrangement of the MT8870D/MT8870D-1 provides a differential-input operational amplifier as well as a
bias source (V
) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback
Ref
resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are
1
connected as shown in Figure 10 with the op-amp connected for unity gain and V
biasing the input at
/
V
.
Ref
2
DD
Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R
.
5
Crystal Oscillator
The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is normally
connected as shown in Figure 10 (Single-Ended Input Configuration). However, it is possible to configure several
MT8870D/MT8870D-1 devices employing only a single oscillator crystal. The oscillator output of the first device in
the chain is coupled through a 30 pF capacitor to the oscillator input (OSC1) of the next device. Subsequent
devices are connected in a similar fashion. Refer to Figure 7 for details. The problems associated with unbalanced
loading are not a concern with the arrangement shown, i.e., precision balancing capacitors are not required.
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Zarlink Semiconductor Inc.