mt8985apr1 Zarlink Semiconductor, mt8985apr1 Datasheet - Page 9

• Manufacturer Part Number: mt8985apr1
• Description: 256 X 256 Channels 8 Tdm Streams At 2.048 Mbps Non-blocking Enhance Digital Switch Edx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

x = Don’t care
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the matrices, and put all other channels into the high impedance state. Care should be taken that no two
connected ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMH
4-0*
BIT
BIT
7-5
6
2
1
0
*
If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the
channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is
output on the channel and stream associated with this location.
CAB4-0*
SAB2-0*
NAME
NAME
CSTo
V/C
MC
OE
Variable/Constant Throughput Delay Mode. This bit is used to select between Variable (LOW)
and Constant Delay (HIGH) modes on a per-channel basis.
Message Channel. When 1, the contents of the corresponding location in Connection Memory
Low are output on the corresponding channel and stream. When 0, the contents of the programmed
location in Connection Memory Low act as an address for the Data Memory and so determine the
source of the connection to the location’s channel and stream.
CSTo Bit. This bit drives a bit time on the CSTo output pin.
Output Enable. This bit enables the output drivers on a per-channel basis. This allows individual
channels on individual streams to be made high-impedance, allowing switch matrices to be
constructed. A HIGH enables the driver and a LOW disables it.
Source Stream Address bits. These three bits are used to select eight source streams for the
connection. Bit 7 of each word is the most significant bit.
Source Channel Address bits 0-4. These five bits are used to select 32 different source channels
for the connection (The ST-BUS stream where the channel is present is defined by bits SAB2-0).
Bit 4 is the most significant bit.
SAB2
7
X
7
SAB1
Figure 5 - Connection Memory High Bits
Figure 6 - Connection Memory Low Bits
V/C
6
6
SAB0
X
5
5
Zarlink Semiconductor Inc.
CAB4
MT8985
4
X
4
9
CAB3
3
X
3
DESCRIPTION
DESCRIPTION
CAB2
MC
2
2
CAB1
CSTo
1
1
CAB0
OE
0
0
Data Sheet
b
0s.