mt8920bs1 Zarlink Semiconductor, mt8920bs1 Datasheet - Page 9

• Manufacturer Part Number: mt8920bs1
• Description: 32 Channels Tdm St-bus To Parallel Bus Access Circuit
• Manufacturer: Zarlink Semiconductor

Data Sheet
Interrupt Mask Register (1/2):
contents of this register masks bits in the Match Byte
Register that are ’don’t care’ bits
In dynamic mode, each bit in this register and the
corresponding bit in the Match Byte Register define
what type of dynamic interrupt is selected. (Refer to
Table 5.)
Interrupt Flag Register (1/2):
the least significant bit in this register is set to 1 to
flag the corresponding path in which the interrupt
occurs.
In dynamic mode this register sets the bits which
reflect the position of the bits in the corresponding
Interrupt Register which caused the interrupt.
Control Register 2
Bits D
Control Register 2
Bits D
Control Register 2
Bits D
µP
µP
µP
1
1
1
= 0, D
= 1, D
= 1, D
Figure 5 - Loopback Configurations
1 - bit masked
0 - bit not masked
0
0
0
= 1
= 0
= 1
Rx0
Tx0
Rx0
Tx0
Rx0
a)
b)
c)
In static mode the
In
static
STo0
STi0
STo0
STi0
STo0
STi0
mode
Interrupt Vector Register
This register shown in Figure 7 is common to both
interrupt paths and stores an 8 bit vector number
which will be output on the data bus when
Interrupt Acknowledge (IACK)
labelled V
Bits IRQ1 and IRQ2 are set by the STPA to indicate
which path caused the interrupt. This creates unique
vectors which are used by the µP to vector to
interrupt service routines. This
bypassed by simply not asserting IACK during
interrupt acknowledged.
D7
V
7
µP
µP
Control Register 2
Bits D
µP
Control Register 2
Bits D
Control Register 2
Bits D
D6
Figure 7 - Interrupt Vector Registers
V
3
3
3
2
6
= 1, D
= 1, D
= 0, D
Figure 6 - STo1 Configurations
- V
D5
2
7
V
2
2
= 0
5
= 1
= 1
Tx0
Rx0
Tx1
Tx0
Rx0
Tx1
Tx0
Rx0
Tx1
are stored by the controlling µP.
D4
V
b)
c)
a)
4
1 Frame Delay
1 Frame Delay
D3
V
3
is asserted.
D2
V
feature
MT8920B
2
IRQ2 IRQ1
D1
STo0
STi0
STo1
STo0
STi0
STo1
STo0
STi0
STo1
may be
D0
Bits
9