zl30105 Zarlink Semiconductor, zl30105 Datasheet - Page 11

• Manufacturer Part Number: zl30105
• Description: Stratum 3 Redundant System Clock Synchronizer For T1/e1/sdh, Advanced Tca And H.110
• Manufacturer: Zarlink Semiconductor

3.0
The ZL30105 is an SDH/PDH Synchronizer for Redundant System Clocks, providing timing and synchronization
signals to interface circuits for the following types of primary rate digital transmission links, see Table 1:
Figure 1 is a functional block diagram of the ZL30105 which is described in the following sections.
3.1
The ZL30105 accepts three simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected
as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs.
The use of the combined REF2 and REF2_SYNC inputs allows for a very accurate phase alignment of the output
frame pulses to the 2 kHz or 8 kHz (multi) frame pulse supplied to the REF2_SYNC input. This feature supports the
implementation of Primary and Secondary Master system clocks in AdvancedTCA or H.110 systems.
3.2
The input references are monitored by three independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
Pin #
56
57
58
59
60
61
62
63
64
•
•
•
•
DS1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E
E1 compliant with ITU-T G.703 and ETSI ETS 300 011
PDH compliant with Telcordia GR-1244-CORE Stratum 3
SDH compliant with ITU-T G.813 option 1 and Telcordia GR-253-CORE
Reference Select Multiplexer (MUX)
Reference Monitor
Functional Description
REF2_SYNC REF2 Synchronization Frame Pulse (Input). This is the 2 kHz or 8 kHz (multi) frame
SEC_MSTR
FASTLOCK
APP_SEL0
TIE_CLR
Name
REF1
REF2
V
IC
DD
Reference (Input). See REF0 pin description.
Reference (Input). See REF0 pin description.
pulse synchronization input associated with the REF2 reference. While the PLL is locked
to the REF2 input reference the output (multi) frame pulses are synchronized to this input.
This pin is internally pulled down to GND.
Secondary Master Mode Selection (Input). A logic low at this pin selects the Primary
Master mode of operation with 1.8 Hz or 3.6 Hz DPLL loop filter bandwidth. A logic high
selects Secondary Master mode which forces the PLL to clear its TIE corrector circuit and
lock to the selected reference using a high bandwidth loop filter and a phase slope
limiting of 9.5 ms/s.
Application Selection (Input). See APP_SEL1 pin description.
Positive Supply Voltage. +3.3 V
Internal Connection. Connect to GND.
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase.
Fast Lock (Input). Set temporarily high to allow the ZL30105 to quickly lock to the input
reference (one second locking time).
Zarlink Semiconductor Inc.
ZL30105
11
DC
nominal
Description
Data Sheet