zl30101 Zarlink Semiconductor, zl30101 Datasheet - Page 23

• Manufacturer Part Number: zl30101
• Description: T1/e1 Stratum 3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

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The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times.
6.0
This section contains ZL30101 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
6.1
Jitter levels on the ZL30101 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30101 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
6.2
The ZL30101 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30101.
6.2.1
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, phase noise, output rise and fall times, output levels and duty cycle.
PLL phase slope limiter,
in-lock phase distance.
Power Supply Decoupling
Master Clock
Applications
Clock Oscillator
1
2
3
4
Table 5 - Typical Clock Oscillator Specification
Frequency
Tolerance
Rise & fall time
Duty cycle
Zarlink Semiconductor Inc.
ZL30101
23
20 MHz
4.6 ppm
< 10 ns
40% to 60%
Data Sheet