zl30116 Zarlink Semiconductor, zl30116 Datasheet - Page 26

• Manufacturer Part Number: zl30116
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
4C
4D
4A
4B
4E
4F
44
45
46
47
48
49
50
51
52
53
54
55
p0_fp1_type
p0_fp1_offset_0
p0_fp1_offset_1
p0_fp1_offset_2
p1_enable
p1_run
p1_freq_0
p1_freq_1
p1_clk0_offset90
p1_clk1_div
p1_clk1_offset90
p1_offset_fine
sdh_enable
sdh_run
sdh_clk_div
sdh_clk0_offset90
sdh_clk1_offset90
sdh_offset_fine
Register
Name
Table 5 - Register Map (continued)
Reset
Value
(Hex)
C1
00
00
00
83
03
00
00
3F
00
00
8F
0F
42
00
00
00
11
SDH Configuration Registers
Zarlink Semiconductor Inc.
P1 Configuration Registers
ZL30116
Bits [7:0] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
Control register for the [7:0] bits of the N of
Control register for the p1_clk0 phase position
Control register for the p1_clk1 frequency
Control register for the p1_clk1 phase position
Control register for the sdh_clk0 phase position
Control register for the sdh_clk1 phase position
Control register for the output/output phase
Control register to select fp1 type
phase offset in multiples of 1/262.144 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
phase offset in multiples of 8 kHz cycles
Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
Control register to generate enable/disable
p1_clk0 and p1_clk1
N*8k clk0
Control register for the [13:8] bits of the N of
N*8k clk0
coarse tuning
selection
coarse tuning
Control register for the output/output phase
alignrment fine tuning
Control register to enable sdh_clk0, sdh_clk1,
sdh_fp0, sdh_fp1 and the SDH PLL
Control register to generate sdh_clk0,
sdh_clk1, sdh_fp0 and sdh_fp1
Control register for the sdh_clk0 and sdh_clk1
frequency selection
coarse tuning
coarse tuning
alignrment fine tuning for sdh path
26
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W