zl30132 Zarlink Semiconductor, zl30132 Datasheet - Page 2

• Manufacturer Part Number: zl30132
• Description: Oc-192/stm-64 Sonet/sdh/10gbe Network Interface Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
Input Reference
Output Clocks and Frame Pulses
Control
Status
Pin #
G8
G7
G5
B1
A3
B4
A1
A2
A4
A7
B8
D8
B2
B3
apll_clk
diff_en
Name
sync0
sync1
sync2
mode
diff_p
diff_n
p_clk
rst_b
p_fp
ref0
ref1
ref2
Type
I/O
O
O
O
O
I
I
I
I
I
u
u
u
u
Input References 2:0 (LVCMOS, Schmitt Trigger). These input references are
available to the DPLL for synchronizing output clocks. All three input references
can lock to any multiple of 8 kHz up to 77.76 MHz including 25 MHz and 50 MHz.
Input ref0 and ref1 have additional configurable pre-dividers allowing input
frequencies of 62.5 MHz and 125 MHz. These pins are internally pulled up to
V
Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger).
These are optional frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled up to V
Differential Output Clock 0 (LVPECL). When in SONET/SDH mode, this output
can be configured to provide any one of the available SONET/SDH clocks
(6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be
configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz,
125 MHz, 156.25 MHz, 312.5 MHz). See “Output Clocks and Frame Pulses” on
page 21 for more details on clock frequency settings.
APLL Output Clock (LVCMOS). This output can be configured to provide any
one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet
clock rates up to 125 MHz. The default frequency for this output is 77.76 MHz.
Programmable Synthesizer - Output Clock (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
Programmable Synthesizer - Output Frame Pulse (LVCMOS). This output can
be configured to provide virtually any style of output frame pulse. The default
frequency for this frame pulse output is 8 kHz.
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
DPLL Mode Select (LVCMOS, Schmitt Trigger). During reset, the level on this
pin determines the default mode of operation for DPLL (Normal=0 or Freerun=1).
After reset, the mode of operation can be controlled directly with this pin, or by
accessing the dpll_modesel register (0x1F) through the serial interface. This pin
is internally pulled up to Vdd.
Differential Output Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output driver is enabled. When set low, the differential driver
is tristated reducing power consumption. This pin is internally pulled up to Vdd.
dd
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Zarlink Semiconductor Inc.
ZL30132
5
Description
dd.
Short Form Data Sheet