zl30131 Zarlink Semiconductor, zl30131 Datasheet - Page 2

• Manufacturer Part Number: zl30131
• Description: Oc-192/stm-64 Sonet/sdh/10gbe Network Interface Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
Input Reference
Output Clocks and Frame Pulses
Pin #
B10
A10
D10
G10
C1
C3
C4
B2
A3
B3
B4
A4
B1
A1
A2
A9
B9
K9
K7
K8
apll_clk0
apll_clk1
p0_clk0
p0_clk1
diff0_p
diff0_n
diff1_p
diff1_n
p0_fp0
Name
sync0
sync1
sync2
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
Type
I/O
I
I
O
O
O
O
O
O
O
u
u
Input References 7:0 (LVCMOS, Schmitt Trigger). These input references are
available to both the Tx DPLL and the Rx DPLL for synchronizing output clocks.
All eight input references can lock to any multiple of 8 kHz up to 77.76 MHz
including 25 MHz and 50 MHz. Input ref0 and ref1 have additional configurable
pre-dividers allowing input frequencies of 62.5 MHz, 125 MHz, and 155.52 MHz.
These pins are internally pulled up to V
Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger).
These are optional frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled up to V
Differential Output Clock 0 (LVPECL). When in SONET/SDH mode, this output
can be configured to provide any one of the available SONET/SDH clocks
(6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be
configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz,
125 MHz, 156.25 MHz, 312.5 MHz). See “Output Clocks and Frame Pulses”
section on page 22 more detail on clock frequency settings.
Differential Output Clock 1 (LVPECL). When in SONET/SDH mode, this output
can be configured to provide any one of the available SONET/SDH clocks
(6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be
configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz,
125 MHz, 156.25 MHz, 312.5 MHz). See “Output Clocks and Frame Pulses”
section on page 22 more detail on clock frequency settings.
APLL Output Clock 0 (LVCMOS). This output can be configured to provide any
one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet
clock rates up to 125 MHz. The default frequency for this output is 77.76 MHz.
APLL Output Clock 1 (LVCMOS). This output can be configured to provide any
one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet
clock rates up to 125 MHz. The default frequency for this output is 19.44 MHz.
Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 100 MHz. The default frequency for this
output is 8.192 MHz.
Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
Zarlink Semiconductor Inc.
ZL30131
5
Description
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dd.
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Short Form Data Sheet