zl30121 Zarlink Semiconductor, zl30121 Datasheet - Page 11

• Manufacturer Part Number: zl30121
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

1.0
The ZL30121 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality
required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to
one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1
The ZL30121 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or
frame pulse synchronization. Table 1 shows a feature summary for both DPLLs.
Modes of Operation
Loop Bandwidth
Phase Slope Limiting
Pull-in Range
Holdover Parameters
Holdover Frequency
Accuracy
Reference Inputs
Sync Inputs
Input Ref Frequencies
Supported Sync Input
Frequencies
Input Reference
Selection/Switching
Hitless Ref Switching
Output Clocks
Output Frame Pulses
Supported Output Clock
Frequencies
DPLL Features
Functional Description
Feature
Free-run, Normal (locked), Holdover
User selectable: 0.1 Hz, 1.7 Hz, 3.5 Hz,
fast lock (7 Hz), 14 Hz, 28 Hz
wideband
User selectable: 885 ns/s, 7.5 2s/s,
61 2s/s, or unlimited
User selectable: 12 ppm, 52 ppm,
83 ppm, 130 ppm
Selectable Update Times: 26 ms, 1 s,
10 s, 60 s, and Selectable Holdover
Post Filter BW: 18 mHz, 2.5 Hz, 10 Hz.
Better than 1 ppb (Stratum 3E) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Ref0 to Ref7
Sync0, Sync1, Sync2
2 kHz, N * 8 kHz up to 77.76 MHz
166.67 Hz, 400 Hz, 1 kHz, 2 kHz,
8 kHz, 64 kHz.
Automatic (based on programmable
priority and revertiveness), or manual
Can be enabled or disabled
diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1,
p0_clk0, p0_clk1, p1_clk0, p1_clk1,
fb_clk.
sdh_fp0, sdh_fp1, p0_fp0, p0_fp1
synchronized to active sync reference.
As listed in Table 4
Table 1 - DPLL1 and DPLL2 Features
2
(890 Hz / 56 Hz / 14 Hz)
DPLL1
Zarlink Semiconductor Inc.
ZL30121
11
1
, or
Free-run, Normal (locked), Holdover
Fixed: 14 Hz
User selectable: 61 2s/s, or unlimited
Fixed: 130 ppm
Fixed Update Time: 26 ms
No Holdover Post Filtering
Better than 50 ppb (Stratum 3) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Ref0 to Ref7
Sync inputs are not supported.
2 kHz, N * 8 kHz up to 77.76 MHz
Sync inputs are not supported.
Automatic (based on programmable
priority and revertiveness), or manual
Can be enabled or disabled
p0_clk0, p0_clk1, p1_clk0, p1_clk1.
p0_fp0, p0_fp1 not synchronized to sync
reference.
As listed in Table 4 for p0_clk0, p0_clk1,
p1_clk0, p1_clk1
DPLL2
Data Sheet