zl30120 Zarlink Semiconductor, zl30120 Datasheet - Page 23

• Manufacturer Part Number: zl30120
• Description: Sonet/sdh/ethernet Multi-rate Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
5A
5B
5C
5D
5E
54
55
56
57
58
59
5F
60
61
62
63
64
65
66
apll_clk1_offset90
apll_offset_fine
apll_fp0_freq
apll_fp0_type
apll_fp0_offset_0
apll_fp0_offset_1
apll_fp0_offset_2
apll_fp1_freq
apll_fp1_type
apll_fp1_offset_0
apll_fp1_offset_1
apll_fp1_offset_2
reserved
reserved
fb_control
fb_offset_fine
reserved
ref_freq_mode_0
ref_freq_mode_1
Register
Name
N * 8 kHz Reference Control
Reset
Value
(Hex)
External Feedback Configuration
A3
00
00
05
23
00
00
00
03
03
00
00
00
53
81
F5
00
00
Zarlink Semiconductor Inc.
ZL30120
Control register for the apll_clk1 phase position
Control register for the output/output phase
Bits [21:16] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
Leave as default
Control register to set whether to use auto
Control register to set whether to use auto
coarse tuning
alignment fine tuning for apll path
Control register to select the apll_fp0 frame
pulse frequency
Control register to select fp0 type
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
phase offset in multiples of 8 kHz cycles
Control register to select apll_fp1 frame pulse
frequency
Control register to select fp1 type
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
phase offset in multiples of 8 kHz cycles
Leave as default
Control register to enable fb_clk and the FB
PLL, int/ext feedback select
Control register for the output/output phase
alignment fine tuning
detect, CustomA or CustomB for ref0 to ref3
detect, CustomA or CustomB for ref4 to ref7
23
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W