zl30157 Zarlink Semiconductor, zl30157 Datasheet

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zl30157

Manufacturer Part Number
zl30157
Description
Two Channel Universal Clock Translator
Manufacturer
Zarlink Semiconductor
Datasheet
Features
JTAG
Ref2
Ref3
Osco
Ref0
Ref1
Osci
Two independent clock channels
Programmable synthesizers generate any clock-
rate from 1 kHz to 720 MHz
One precision synthesizers generate clocks with
jitter below 0.7 ps RMS for 10 G PHYs
One general purpose synthesizers generate a wide
range of digital bus clocks
Programmable digital PLLs synchronize to any
clock rate from 1 kHz to 720 MHz
Flexible two-stage architecture translates between
arbitrary data rates, line coding rates and FEC
rates
Digital PLLs filter jitter from 14 Hz, 28 Hz, 56 Hz,
112 Hz, 224 Hz, 448 Hz or 896 Hz
Automatic hitless reference switching and digital
holdover on reference fail
Four reference inputs configurable as single ended
or differential
Eight LVPECL outputs and four LVCMOS outputs
ZL30157
Single Ended
Single Ended
Single Ended
Single Ended
Master Clock
Differential /
Differential /
Differential /
Differential /
JTAG
Reference Monitors
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
pwr_b
State Machine
Copyright 2011, Zarlink Semiconductor Inc. All Rights Reserved.
Fr= Br
Fr= Br
DPLL0
DPLL1
0
1
*Kr
*Kr
Figure 1 - Functional Block Diagram
0
1
*Mr
*Mr
0
1
GPIO
/Nr
/Nr
Configuration
and Status
0
1
Zarlink Semiconductor Inc.
SPI / I
Two
2
C
1
Clock Generator 0 (Precision)
Clock Generator 1 (General Purpose)
Fs= Bs
Fs= Bs
Applications
Channel Universal Clock Translator
Synthesizer 0
Synthesizer 1
Eight outputs configurable as LVCMOS or
LVDS/LVPECL/HCSL
Operates from a single crystal resonator or clock
oscillator
Configurable via SPI/I2C interface
10 Gigabit line cards
Synchronous Ethernet, 10 GBASE-R and
10 GBASE-W
OTN multiplexers and transponders
SONET/SDH, Fibre Channel, XAUI
0
ZL30157GGG
ZL30157GGG2
1
*Ks
*Ks
0
1
*16*Ms
*8*Ms
1
0
/Ns
/Ns
*Pb Free Tin/Silver/Copper
1
0
Ordering Information
Div A
Div B
Div C
Div D
Div A
Div B
Div C
Div D
Div A
Div B
Div C
Div D
Div A
Div B
Div C
Div D
-40
100 Pin CABGA
100 Pin CABGA*
o
C to +85
Short Form Data Sheet
Single Ended
Single Ended
Single Ended
Single Ended
Differential /
Differential /
Differential /
Differential /
LVCMOS
LVCMOS
LVPECL
LVPECL
2 x Differential
2 x LVCMOS
2 x LVCMOS
2 x Differential
4 x LVPECL
4 x LVPECL
or 4 x Single
or 4 x Single
Outputs
Outputs
Ended
Ended
o
C
ZL30157
Trays
Trays
hpdiff0_p/n
hpdiff1_p/n
hpdiff2_p/n
hpdiff3_p/n
hpdiff4_p/n
hpdiff5_p/n
hpdiff6_p/n
hpdiff7_p/n
hpoutclk0
hpoutclk1
hpoutclk2
hpoutclk3
outclk0
outclk1
outclk2
outclk3
outclk4
outclk5
outclk6
outclk7
March 2011

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zl30157 Summary of contents

Page 1

... Synthesizer 1 Fs= Bs *Ks *8*Ms / Configuration and Status 2 GPIO SPI / I C Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30157 Short Form Data Sheet March 2011 Ordering Information 100 Pin CABGA Trays 100 Pin CABGA* Trays +85 C hpdiff0_p/n hpdiff1_p/n Outputs hpdiff2_p/n ...

Page 2

... The ZL30157 integrates 2 independent digital PLLs, accepts 4 input references and generates 12 programmable clock outputs. One precision synthesizers generates clocks with jitter performance that can directly drive 10 G PHY devices ...

Page 3

... Mechanical Drawing ZL30157 3 Zarlink Semiconductor Inc. Short Form Data Sheet ...

Page 4

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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