zl30410 Zarlink Semiconductor, zl30410 Datasheet
zl30410
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zl30410 Summary of contents
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... The filtering characteristics of the PLL are hardware pin selectable and they do not require any external adjustable components. The ZL30410 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation. C20i ...
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... JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 ZL30410 Switching Between Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . 19 5.1.3 Single 8 kHz Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL 20 5.1.4 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL 5.1.5 Reference Switching (RefSel): NORMAL --> ...
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... Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections for 80-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - Core PLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - C34/C44, C155o Clock Generation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - ZL30410 State Machine Figure 6 - Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7 - Primary and Secondary Reference Out of Range Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8 - Transition from Free-run to Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9 - Automatic Entry into Auto Holdover State and Recovery into Normal Mode ...
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... Table 1 - Operating Modes and States Table 2 - Filter Characteristic Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3 - Reference Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ZL30410 List of Tables 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Changes from March 2006 Issue to November 2006 Issue. Page, section, figure and table numbers refer to this current issue. Page Item 28 Figure 18 Changes from February 2006 Issue to March 2006 Issue. Page, section, figure and table numbers refer to this current issue. Page Item 1 Ordering Information Box 2.0 ZL30410 Pinout 2.1 Pin Connections SECOR OE NC RESET GND ...
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... The logic level at this input is sampled by the rising edge of the F8o frame pulse. 19 MS2 Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30410 mode of operation (Normal, Holdover or Free-run), see Table 1 on page 16 for details. The logic level at this input is sampled by the rising edge of the F8o frame pulse. ...
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... PRI Primary Reference (Input). This input is used as a primary reference source for synchronization. The ZL30410 can synchronize to the falling edge of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz clock. In Hardware Control, selection of the input reference is based upon the RefSel control input ...
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... Clock 20 MHz (5 V tolerant input). This pin is the input for the 20 MHz Master Clock Oscillator. The clock oscillator should be connected directly (not AC coupled) to the C20i input and it must supply clock with duty cycle that is not worse than 40/60%. 52 GND Digital Ground ZL30410 Description 8 Zarlink Semiconductor Inc. Data Sheet ...
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... The internal reset is performed by forcing RESET pin low for a minimum of 1 µs after the C20 Master Clock is applied to pin C20i. This operation forces the ZL30410 internal state machine into a RESET state for a duration of 625 µs. ...
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... GR-1244 for Stratum 4E and 4 Clocks When locked to a G.813 Option 1 and 2 or SONET Stratum 3 quality clock the ZL30410 generates clocks that also meet SONET Stratum 3 or G.813 Option 1 and 2 requirements. The Core PLL supports three mandatory modes of operation: Free-run, Normal (Locked) and Holdover. Each of these modes places specific requirements on the building blocks of the Core PLL. • ...
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... When the ZL30410 finishes locking to a reference an arbitrary phase difference will remain between its output clocks and its reference; this phase difference is part of the normal operation of the ZL30410 desired, the output clocks can be brought into phase alignment with the PLL reference by using the RefAlign control pin. ...
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... Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference If the ZL30410 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought into phase alignment with the PLL reference by using the RefAlign control pin according to the following procedure: • ...
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... C155 : 155.52 MHz clock with nominal 50% duty cycle. The ZL30410 provides the following frame pulses (see Figure 15 "ST-BUS and GCI Output Timing" for details). All frame pulses have the same 125µs period (8kHz frequency): - F0o : 244 ns wide, logic low frame pulse ...
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... External transition Reset State The Reset State must be entered when ZL30410 is powered-up. In this state, all arithmetic calculations are halted, and clocks are stopped. The Reset state is entered by pulling the RESET pin low for a minimum of 1 µs. When the RESET pin is pulled back high, internal logic starts a 625 µs initialization process before switching into the Free-run state (MS2, MS1 = 10) ...
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... Both of them force the Core PLL to transition into and out of the Auto Holdover state. The ZL30410 State Machine is driven by controlling the mode select pins MS2, MS1 and RefSel. In order to avoid synchronization problems, the State Machine has built-in basic protection that does not allow switching the Core PLL into a state where it cannot operate correctly e ...
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... Control Interface The ZL30410 has a built-in simple control interface that makes it suitable for application that can provide only a limited amount of supervision. This allows for building multi-service line cards without extensive programming. The complete set of control and status pins is shown in Figure 6 - Control Interface on page 16. ...
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... Status Pins The ZL30410 has four dedicated status pins for indicating modes of operation and quality of the Primary and Secondary reference clocks. These pins are listed below: LOCK. This output goes high after the ZL30410 has completed its locking sequence (see section 2.2.3 for details). ...
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... ZL30410 Switching Between Clock Modes The ZL30410 is designed to transition from one mode to the other driven by the internal State Machine or by external control. The following examples present a couple of typical scenarios of how the ZL30410 can be employed in network interface line cards. ...
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... The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Line Card loses its single reference clock unexpectedly. The sequence starts with the reference clock transitioning from OK --> FAIL at a time when ZL30410 operates in Normal mode (as is shown in Figure 10). This failure is detected by the active Acquisition PLL based on the following FAIL criteria: • ...
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... Normal state. When the Master Clock Oscillator accuracy exceeds ±4.6 ppm range (leading to inaccurate internal out-of-range detection) then an external method for detecting the presence of the clock should be employed to switch the ZL30410 into Normal state (0.1 sec after detecting the presence of a valid 8 kHz reference). ...
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... Holdover state to guarantee “hit-less” recovery (for details see section 5.1.3 on page 20). If the reference clock failure persists for a period of time that exceeds the system design limit, the system control processor may initiate a reference switch. If the secondary reference is available the ZL30410 will briefly switch into Holdover mode and then transition to Normal mode. ...
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... Semi-automatic transition, which involves changing RefSel input to select a secondary reference clock without changing the mode select inputs MS2,MS1=00 (Normal mode). This forces the ZL30410 to momentarily transition through the Holdover state and automatically return to Normal mode after synchronizing to a secondary reference clock. ...
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... Voltages are with respect to ground (GND) unless otherwise stated. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ZL30410 ZL30410 Figure 13 - Power Supply Filtering Symbol ...
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... Rise and fall threshold voltage Low * Voltages are with respect to ground (GND) unless otherwise stated. * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case conditions (over T ZL30410 Symbol Min V 3.0 DD ...
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... F0o pulse width low (nom 244 ns) 9 F8o to F0o delay 10 C4o pulse width low 11 F8o to C4o delay 12 C2o pulse width low 13 F8o to C2o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30410 Timing Reference Points Symbol Min. Max F16L ...
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... AC Electrical Characteristics - DS1 and DS2 Clock Timing* Characteristics 1 C6o pulse width low 2 F8o to C6o delay 3 C1.5o pulse width low 4 F8o to C1.5o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30410 t C16L t C8L t C4L t C2L Figure 15 - ST-BUS and GCI Output Timing Symbol Min ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. t C155L C155oP C19DLH C19o tc = 51.44 ns Note: Delay is measured from the rising edge of C155P clock (single ended) at 1.25 V threshold to the rising and falling edges of C19o clock at V ZL30410 t t C6L C6D t t C1.5D C1.5L Figure 16 - DS1 and DS2 Clock Timing Symbol Min ...
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... PRI/SEC 2.048 MHz tc = 488.28 ns PRI/SEC 19.44 MHz tc = 51.44 ns C19o tc = 51.44 ns F8o tc = 125 µs Note: Delay time measurements are done with jitter free input reference signals. Figure 18 - Input Reference to Output Clock Phase Alignment ZL30410 Symbol Min Max t 100 R8W R8D t 100 R1 ...
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... C11o clock pulse width high 3 C34o clock pulse width high 4 C8.5o clock pulse width high * Supply voltage and operating temperature are as per Recommended Operating Conditions. C44o tc = 22.35 ns C11o tc = 89.41 ns C34o tc = 29.10 ns C8. 116.39 ns ZL30410 Symbol Min. t 100 S t 100 Symbol Min. ...
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... PRI ⇒ SEC, SEC ⇒ PRI 9 Switching from Normal mode to Holdover mode 10 Switching from Holdover mode to Normal mode Output Phase Slope Loop Filter * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30410 Min. Typ. Max. -12 -12 70x10 160x10 Hz/Hz -12 -12 ...
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... Equivalent Limit in limit in Typ. UI time domain 0.07 UIpp 45.3 0.63 0.5 UIpp 324 0.93 31 Zarlink Semiconductor Inc. Data Sheet T1.105.03 conformance ZL30410 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns P-P ns RMS ns P-P C19 Clock Output ns P-P ns P-P ns RMS ns P-P ZL30410 Jitter Generation Performance Units Notes C1.5 Clock Output ns P-P ns P-P ...
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... Limit in limit in Typ. UI time domain C16, C8, C4 and C2 Clock Outputs 0.05 UIpp 24.4 0.56 32 Zarlink Semiconductor Inc. Data Sheet ZL30410 Jitter Generation Performance Units Notes C6 Clock Output ns P-P ZL30410 Jitter Generation Performance Units Notes C44 Clock Output ns P-P ns P-P conformance ZL30410 Jitter Generation Performance Units Notes ns P-P ...
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... Jitter Generation Requirements Jitter Interface Measurement Filter 1 E3 100 Hz to 800 kHz 34368 kbps * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30410 G.751 conformance ZL30410 Jitter Generation Equivalent Limit in limit in Typ. UI time domain 0.05 UIpp 1.45 0.64 33 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps 100 kHz 2048 kbps 10 DS1 kHz 1.544 Mbps * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30410 G.812 conformance ZL30410 Jitter Generation Equivalent Limit in limit in Typ. UI time domain 0.1 UIpp 0.643 0.325 0.5 UIpp 3.215 0.448 ...
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... MHz 155.52 4 500 Hz to 1.3 MHz Mbps 100 kHz 2048 kbps * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30410 G.813 conformance (Option 1) ZL30410 Jitter Generation Equivalent Limit in limit in Typ. UI time domain 0.1 UIpp 0.643 0.325 0.5 UIpp 3.215 ...
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... UIpp 3.215 0.448 0.1 UIpp 0.643 0.390 0.5 UIpp 3.215 0.512 0.075 UIpp 0.482 0.390 0.5 UIpp 3.215 0.512 36 Zarlink Semiconductor Inc. Data Sheet ZL30410 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns P-P C155 Clock Output ns P-P ns P-P C19 Clock Output ns P-P ns P-P C19 Clock Output ...
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... C6o (6.312 MHz) 5 C8o (8.192 MHz) 6 C8.5o (8.592 MHz) 7 C11o (11.184 MHz) 8 C16o (16.384 MHz) 9 C19o (19.44 MHz) 10 C34o (34.368 MHz) 11 C44o (44.736 MHz) 12 C155o (155.52 MHz) 13 F0o (8 kHz) 14 F8o (8 kHz) 15 F16o (8 kHz) ZL30410 Typ. Typ. ( 0.0042 2.71 0.0019 0.95 0.0037 0.92 0.0179 2.84 0.0081 0.99 0.0222 2.58 0.0295 2.64 ...
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