zl30406 Zarlink Semiconductor, zl30406 Datasheet
zl30406
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zl30406 Summary of contents
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... Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. SONET/SDH Clock Multiplier PLL Ordering Information ZL30406QGC ZL30406QGG1 Description The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) and SONET networking equipment. The ZL30406 generates very ...
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... OC-CLKoP 6 GND 7 VCC2 ZL30406 EP_GND ZL30406 Figure 2 - TQFP 64 pin (Top View) Updated Ordering Information. Description Ground. 0 volt. Positive Analog Power Supply. +3.3 V ±10% Positive Analog Power Supply. +3.3 V ±10% SONET/SDH Clock (CML Output). These outputs provide a programmable differential CML clock at 19 ...
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... C19 Reference Input (CMOS Input). This pin is a single-ended input reference source used for synchronization. This pin accepts 19.44 MHz. 29 VDD Positive Digital Power Supply. +3.3 V ±10% 30 GND Ground. 0 volt internal bonding Connection. Leave unconnected. 32 GND Ground. 0 volt. ZL30406 Description 3 Zarlink Semiconductor Inc. Data Sheet and ...
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... C77oP-A C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated 63 C77oN-A to decrease supply current. 64 GND Ground. 0 volt 65 EP_GND Exposed die Pad Ground. 0 volt (connect to GND) ZL30406 Description 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30406 is shown in Figure 1 and a brief description is presented in the following sections. 1.1 Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two ...
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... If any of the LVPECL outputs are disabled they must be left open without any terminations. The output clock frequency of the OC-CLKo CML differential output clock is selected with FS1-2 pins as shown in the following table. Table 2 - OC-CLKo Clock Frequency Selection ZL30406 Output Clocks Output Enable Pins C77oP/N-A ...
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... The ZL30406 functionality and performance complements the entire family of the Zarlink’s advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating at OC-48/STM-16 rate (2.5 Gbit/s). The ZL30406 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 4) ...
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... The ZL30406 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 5). C19i R = 680 : 820 PRI SEC Synchronization Reference RSEL Clocks LOCK HOLDOVER C20i 20 MHz TCXO Note: Only main functional connections are shown ZL30406 ...
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... The CMLP/N output provides a differential CML/LVDS compatible clock at 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz selected with FS1-2 pins. The output drivers require load at the terminating end if the receiver is CML type. VCC ZL30406 CML Driver GND ZL30406 +3.3 V 0.1 uF Z=50 : C77oP-A Z=50 : C77oN-A Typical resistor values 130 :, R2 =82 : Figure 6 - LVPECL to LVPECL Interface +3 ...
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... Driver GND ZL30406 +3 Z=50 : OC-CLKoP Z=50 : OC-CLKoN 10 nF Typical resistor values k Figure 8 - LVDS Termination +3.3 V 0.1 uF ZL30406 Z=50: OC-CLKoP 77.76MHz Z=50 : OC-CLKoN Typical resistor values =130 : Figure 9 - CML to LVPECL Interface 10 Zarlink Semiconductor Inc. Data Sheet (common mode voltage) CM VCC=+3.3 V LVDS ...
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... Tristating LVPECL Outputs The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC- 12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required, a user can disable unused LVPECL outputs on the ZL30406 by pulling the corresponding enable pins low. When disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0 ...
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... All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same 2. Select Ferrite Bead with I DC Figure 11 - Power Supply and BIAS circuit filtering ZL30406 0.1 uF 0.1uF GND VCC1 2 VCC 4 0 GND VCC2 8 ZL30406 + 0 GND 10 GND BIAS 0 0.1uF 0.1uF > ...
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... Figure 6) 3 Incremental Supply Current to CML driver (driver enabled and terminated, see Figure 7) 4 CMOS: High-level input voltage 5 CMOS: Low-level input voltage 6 CMOS: Input leakage current, C19i ZL30406 ‡ Sym Min TBD DDR CCR V -0.5 PIN I -0.5 PIN ...
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... LVPECL outputs. More than 25% of this current flows LVPECL outside the chip and it does not contribute to the internal power dissipation. Note 2: LVPECL outputs terminated with Z Note 3: CML outputs terminated with Z T ZL30406 Sym. Min. Typ. I 300 B-PU I ...
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... Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i (19.44 MHz) C19o (19.44 MHz) C77oA (77.76 MHz) Note: All output clocks have nominal 50% duty cycle. Figure 13 - C19i Input to C19o and C77o Output Timing ZL30406 ‡ Sym CMOS LVPECL V 0.5V 0.5V T-CMOS ...
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... Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i (19.44 MHz) OC-CLKo(19) (19.44 MHz) OC-CLKo(38) (38.88 MHz) OC-CLKo(77) (77.76 MHz) OC-CLKo(155) (155.52 MHz) Note: All output clocks have nominal 50% duty cycle. Figure 14 - C19i Input to OC-CLKo Output Timing ZL30406 ‡ Sym. Min. Typ. t 3.2 OC-CLK19D t 3.0 OC-CLK38D t 2.7 ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C77oA C77oB C77oC C77oD Note: All output clocks have nominal 50% duty cycle. Figure 15 - C77oB, C77oC, C77oD Outputs Timing ZL30406 ‡ Sym. Min. Typ. t 100 C77D-AB ...
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... Min. Max. Units ±1000 ppm 300 ms ZL30406 Jitter Generation Performance Equivalent Limit in limit in time UI domain 0.1 UIpp 40.2 0.01UI 4.02 RMS 0.1 UIpp 161 0.01UI 16.1 RMS ZL30406 Jitter Generation Performance Equivalent Limit in limit in time UI domain 0.1 UIpp 40 0.5UIpp 201 - - 0.1 UIpp 161 - - 0.5 UIpp 804 - - 18 Zarlink Semiconductor Inc. ...
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... STM-16 12 kHz - 20 MHz 4 STM-4 12 kHz - 5 MHz † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: R =8.2 k:C =470 ZL30406 ZL30406 Jitter Generation Performance Limit in Equivalent limit in time domain UI 0.1 UIpp 40 0.5 UIpp 201 - - 0 ...
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... Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...