zl30312 Zarlink Semiconductor, zl30312 Datasheet
zl30312
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zl30312 Summary of contents
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... Monitors sync0 sync1 sync2 Figure 1 - ZL30312 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved. Combined Synchronous Ethernet and IEEE1588 Network Synchronization ZL30312GKG ZL30312GKG2 • ...
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... Synchronous Ethernet and IEEE1588 protocols, either alone or in combination. The ZL30312 is a member of a family of footprint-compatible devices offering the full range of features required for timing and synchronization across the packet network. These devices facilitate design of a flexible card that can be upgraded as required by simply placing another member of the same family ...
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... When using ToP technology, the device is designed to meet ANSI standard T1.101 and ITU-T standards G.823 and G.824 for synchronization distribution. It maintains a mean frequency accuracy of better than ±10 ppb and time alignment of better than ±1 μs when operated over a suitable network. ZL30312 Description conventional PLL behaviour, e ...
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... Zarlink Semiconductor 2006 All rights reserved ISSUE CDCA ACN 24Aug06 DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...