mt90823ap1 Zarlink Semiconductor, mt90823ap1 Datasheet - Page 18

• Manufacturer Part Number: mt90823ap1
• Description: 2048 X 2048 Channels Selectable Rate 2, 4, 8 Mbps 3.3 V Non-blocking Large Digital Switch Ldx
• Manufacturer: Zarlink Semiconductor

15 - 13
10 - 0
Bit
12
11
15
0
Read Address:
Reset Value:
14
0
FD10-0
Unused
Name
FD11
CFE
13
0
CFE
12
Table 10 - Frame Alignment (FAR) Register Bits
FD11
11
Must be zero for normal operation.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and bits FD10 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to
0.
Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is
sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase
(FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle.
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the IMS register changes from 1 to 0. (FD10 = MSB, FD0 = LSB)
02
0000
H
FD10
10
,
H
.
FD9
Zarlink Semiconductor Inc.
9
MT90823
FD8
8
18
FD7
7
FD6
6
Description
FD5
5
FD4
4
FD3
3
FD2
2
FD1
1
Data Sheet
FD0
0