mt90863al1 Zarlink Semiconductor, mt90863al1 Datasheet - Page 33

• Manufacturer Part Number: mt90863al1
• Description: 2,048 X 512 Channel 3.3 V Rate Conversion Digital Switch Rcdx , H.100 Compatible
• Manufacturer: Zarlink Semiconductor

7.0
The MT90863 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. This standard specifies a
design-for-testability technique called Boundary-Scan Test (BST). The operation of the boundary-scan circuitry is
controlled by an external Test Access Port (TAP) Controller.
7.1
The Test Access Port (TAP) accesses the MT90863 test functions. It consists of three input pins and one output pin
as follows:
•
•
•
•
•
Note 1: If bit 12 (LMC) of the corresponding local connection memory location is 1 (device in message mode), then these entire 8
bits (Bit7-0) are output on the output channel and stream associated with this location.
(Note1)
(Note1)
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not
driven from an external source.
Test Data Input (TDi)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDo)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo driver is
set to a high impedance state.
Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VDD.
15-2
Bit
1,0
15
Test Access Port (TAP)
JTAG Support
0
14
0
LSR1, LSR0
Unused
13
Name
0
12
0
Table 22 - Local Connection Memory High Bits
11
0
Must be zero for normal operation.
Local Sub-rate Switching Bit
When 11
When 10
When 01
When 00
10
0
9
0
Zarlink Semiconductor Inc.
MT90863
Bit7-6 will be the output of the subrate switching stream
Bit5-4 will be the output of the subrate switching stream
Bit3-2 will be the output of the subrate switching stream
Bit1-0 will be the output of the subrate switching stream
8
0
33
7
0
6
0
Description
5
0
4
0
3
0
2
0
LSR1
1
Data Sheet
LSR0
0