mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 17

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

0 [00]
1 [01]
2 [10]
3 [11]
5 [101]
6 [110]
7 [111]
Mode
[bits]
Mode [bits]
Bit
7
6
5
4
3
2
1
0
SEC8K >DPLL
EX8KA >DPLL
EX8KB >DPLL
APLL source
DACK1
DACK0
EX8KB
EX8KA
INV_CLK8
INV_CLK4
INV_CLK2
INV_FRM
16.384MHz
8.192MHz
4.096MHz
RESERVED
Table 9 - PLL_MODE Bits (control PLL and frame synchronization)
Name
Table 10 - XCLK_SEL bits (control divide ratio of X1 clock)
X1 =
Table 11 - Local Clock Control (LOC_CLK) Register
Frame Sync.
frame sync.
to SEC8K
frame sync.
to EX8KA
frame sync.
to EX_8KB
Figure 7 - Serial Mode (SER_MODE) Register
7
X1 must be 16.384 MHz when PLL is in modes 1-3 or 5-7
Read-only, reads logic value on DACK1 pin
Read-only, reads logic value on DACK0 pin
Read-only, reads logic value on EX8KB pin
Read-only, reads logic value on EX8KA pin
When set, inverts 8.192 MHz CLK8 output pin
When set, inverts 4.096 MHz CLK4 output pin
When set, inverts 2.048 MHz CLK2 output pin
When set, inverts FRAME output signal
6
RESERVED
Zarlink Semiconductor Inc.
5
FMIC as MVIP Master (Slaved to external 8 kHz)
• DPLL is selected as the source to the APLL. Input to the DPLL
• State machine is synchronized to external 8 kHz
• XCLK_SEL must be programmed to mode 0.
• MVIP_MST bit in MCS must be set.
is either SEC8K,EX8KA/EX8KB.
(SEC8K/EX8KA/B); that is, FRAME signal is freq locked and
phase aligned with external 8 kHz.
MT90810
4
17
Description
3
Description
2
SER_CNFG
1
Bit Function
Comments
0
Function
Data Sheet