mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 24

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

Phase Lock Loop (PLL)
The MT9074 contains a PLL, which can be locked to either an input 4.096 Mhz clock or the extracted line clock.The
PLL will attenuate jitter from less than 2.5 Hz and roll-off at a rate of 20 dB/decade. Its intrinsic jitter is less than 0.02
UI. The PLL will meet the jitter transfer characteristics as specified by ATT document TR 62411 and the relevant
recommendations as shown in Figure 11.
Clock Jitter Attenuation Modes
MT9074 has three basic jitter attenuation modes of operation, selected by the BS/LS and S/FR control pins.
Referring to the mode names given in Table 5 the basic operation of the jitter attenuation modes are:
•
•
•
In System Bus Synchronous mode pins C4b and F0b are always configured as inputs, while in the Line
Synchronous and Free-Run modes C4b and F0b are configured as outputs.
In System Bus Synchronous mode an external clock is applied to C4b. The applied clock is dejittered by the internal
PLL before being used to synchronize the transmitted data. The clock extracted (with no jitter attenuation
performed) from the receive data can be monitored on pin E1.5o.
In Line Synchronous mode, the clock extracted from the receive data is dejittered using the internal PLL and then
output on pin C4b. Pin E1.5o provides the extracted receive clock before it has been dejittered. The transmit data is
synchronous to the clean receive clock.
In Free-Run mode the transmit data is synchronized to the internally generated clock. The internal clock is output
on pin C4b. The clock signal extracted from the receive data is not dejittered and is output directly on E1.5o.
Depending on the mode selection above, the PLL can either attenuate transmit clock jitter or the receive clock jitter.
Table 5 shows the appropriate configuration of each control pin to achieve the appropriate mode and Jitter
attenuation capability of the MT9074
The Digital Interface
T1 Digital Interface
In T1 mode DS1 frames are 193 bits long and are transmitted at a frame repetition rate of 8000 Hz, which results in
an aggregate bit rate of 193 bits x 8000/sec= 1.544 Mbits/sec. The actual bit rate is 1.544 Mbits/sec +/-50 ppm
optionally encoded in B8ZS format. The Zero Suppression control register (page 1, address 15H,) selects either
B8ZS encoding, forced one stuffing or alternate mark inversion (AMI) encoding. Basic frames are divided into 24
time slots numbered 1 to 24. Each time slot is 8 bits in length and is transmitted most significant bit first (numbered
bit 1). This results in a single time slot data rate of 8 bits x 8000/sec. = 64 kbits/sec.
System Bus Synchronous Mode
Line Synchronous Mode
Free-Run Mode
Table 5 - Selection of Clock Jitter Attenuation Modes using the M/S and MS/FR Pins
Line Synchronous
Synchronous
Mode Name
System Bus
Free-Run
Zarlink Semiconductor Inc.
BS/LS
1
0
x
MT9074
24
S/FR
1
1
0
PLL locked to E1.5o
PLL free - running.
PLL locked to C4b
Note
Data Sheet