s19261 Applied Micro Circuits Corporation (AMCC), s19261 Datasheet

s19261

Manufacturer Part Number

s19261

Description

Sts-192 Sonet/sdh/fec/gbe/fc 16-bit Demux With Edc

Manufacturer

Applied Micro Circuits Corporation (AMCC)

Datasheet

1.S19261.pdf (2 pages)

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S19261

STS-192 SONET/SDH/FEC/GbE/FC 16-bit DeMux with EDC

Features

• Operational from 9.9 Gbps to 11.32 Gbps

• On-chip High-Frequency PLLs for Clock

• 16-bit LVDS Parallel Data Path

• RX Lock Detect Indicator

• LOS/RSSI

• ISI compensation. Tolerates additional

• Tolerates up to 34” of Standard FR-4 Mate-

• Adaptive Post-Amplifier Offset Adjust

• Phase Adjust of -0.11 to +0.085 UI

• Reference Clock input with Divide by 16,

• Capability to Interface with Single-Ended

• Input Sensitivity of 10 mV p-p (one wire or

• -40°C to 85°C Industrial Temperature

• Supports MDIO, I2C and SPI serial inter-

• Complies with applicable OIF SFI-4 Phase

• 2000 V ESD rating on low speed pins, 1000

• 15 mm x 15 mm

• 830 mW typical

• JTAG support

Applications

• SONET/SDH and 10GbE-Based Transmis-

• Broad-Band Cross-Connects

• Fiber Optic Test Equipment

• 300 pin MSA Modules

Recovery and Clock Gen.

350 ps/nm of chromatic dispersion with

an OSNR penalty of 1.0dB over a tradi-

tional demux

rial

64 or 66 of the Incoming Serial Data Rate

or Differential TIAs (Center Tap Option)

two wire) at 10

Range

face

1, Telcordia/ITU-T, 300-pin MSA, IEEE

802.3ae and XFP MSA Standards

V on high speed I/Os

sion Systems

KHATANGA

RUBICON

MEKONG

GANGES

HUDSON

AMCC

-12

, 0.8 mm pitch package

BER

S19261

AMCC

Description

The S19261 DeMux chip is a fully integrated de-

serialization SONET STS-192/10 Gigabit

Ethernet/Fiber Channel DeMux with Electronic

Dispersion Compensation (EDC). This device

can be used to compensate channel

impairments caused by Single Mode Fiber

(SMF) and copper medium. The chip performs

all necessary serial-to-parallel functions in

conformance with SONET/SDH, 10 Gigabit

Ethernet (10GbE) and 10 Gigabit Fibre Channel

(10GFC) transmission standards. The figure

below shows a typical network application. The

other application block diagrams are shown on

page 2.

The chip can be used with 155.52 MHz or

622.08 MHz (or equivalent FEC/10GbE/10GFC

rates) reference clock in support of existing

system clocking schemes. The low-jitter LVDS

parallel interface guarantees compliance with

the bit-error rate requirements of the Telcordia

and ITU-T standards.

Overview

The S19261 De-Mux incorporates SONET/SDH/

10GbE/10GFC deserialization functions. This

chip can be used to implement the front end of

SONET/10GbE/10GFC equipment, which

consists primarily of the serial receive interface.

The chip includes serial-to-parallel conversion

and system timing.

TIA

System Block Diagram with the S19261

ORX

OTX

AMCC Suggested Interface Devices

The sequence of operations is as follows:

Receiver Operations

Internal clocking and control functions are

transparent to the user.

RUBICON

(S19227)

GANGES III (S19202)

Hudson 2.0

(S19203)

KHATANGA

(S19205)

MEKONG

(S19204)

S19233

• Serial input to post-Amplifier

• ISI compensation

• LOS and RSSI

• Threshold and phase adjustment for improved BER

• Clock and data recovery

• Serial-to-parallel conversion

• 16-bit parallel data and clock output

10G Clk

data

P R O D U C T B R I E F

S19260

AMCC

OC-192/48/12/3 DW/FEC/PM and

ASYNC Mapper Device with Strong

FEC

STS-192 POS/ATM SONET/SDH

Mapper

Variable Rate DW/FEC/PM

STS-192c SONET/SDH Framer/Map-

per w/Integrated MAC

STS-192 Pointer Processor

Dual CDR imbedded in XFP module

KHATANGA

RUBICON

HUDSON

MEKONG

GANGES

AMCC

Related parts for s19261

s19261 Summary of contents

Page 1

... S19261 STS-192 SONET/SDH/FEC/GbE/FC 16-bit DeMux with EDC Features Description • Operational from 9.9 Gbps to 11.32 Gbps The S19261 DeMux chip is a fully integrated de- • On-chip High-Frequency PLLs for Clock serialization SONET STS-192/10 Gigabit Recovery and Clock Gen. Ethernet/Fiber Channel DeMux with Electronic • 16-bit LVDS Parallel Data Path • ...

Page 2

... Enable Adaptive Post-Amplifier Offset Control Enable Adaptive ISI Mitigation Disable EDC / 10G Clock MDIO/I2C /SPI AMCC ASIC 16 OR S19260 XFP MODULE FRAMER 16 OR S19261 FEC Compensates up to 24" of FR-4 Figure 2. XFP Application Block Diagram 16 C 300 MSA MODULE Laser O AMCC Laser N S19260 Driver ...

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