s19260 Applied Micro Circuits Corporation (AMCC), s19260 Datasheet

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s19260

Manufacturer Part Number
s19260
Description
Sts-192 Sonet/sdh/fec/gbe/fc 16-bit Mux With 10g Clock
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
S19260
STS-192 SONET/SDH/FEC/GbE/FC 16-bit Mux with 10G Clock
Features
• Operational from 9.9 Gbps to 11.32 Gbps
• On-chip High-Frequency PLLs for Clock
• 16-bit LVDS Parallel Data Path
• TX Lock Detect Indicator
• Reference Clock input with Divide by 16,
• Internal, Self-Initializing FIFO to Decouple
• Programmable TSD Output Differential
• 10 G Transmitter Serial Clock Output
• Duo Binary Encoding
• -40°C to 85°C Industrial Temperature
• Supports MDIO, I2C and SPI serial inter-
• Complies with applicable OIF SFI-4 Phase
• 2000 V ESD rating on low speed pins,
• 15 mm x 15 mm
• 560 mW typical
• JTAG support
Applications
• SONET/SDH and 10GbE-Based Transmis-
• Broad-Band Cross-Connects
• Fiber Optic Test Equipment
• 300 pin MSA Modules
Recovery and Clock Gen.
64, or 66 of the Incoming Serial Data Rate
Transmit Clocks
Swing
Range
face
1, Telcordia/ITU-T, 300-pin MSA, IEEE
802.3ae and XFP MSA Standards
1000 V on high speed I/Os
sion Systems
KHATANGA
RUBICON
GANGES
HUDSON
MEKONG
AMCC
2
, 0.8 mm pitch package
16
S19261
AMCC
Description
The S19260 Mux chip is a fully integrated
serialization SONET STS-192/10 Gigabit
Ethernet/Fiber Channel device with 10G clock
output. This device can be used to compensate
channel impairments caused by Single Mode
Fiber (SMF) and copper medium. The chip
performs all necessary parallel-to-serial
functions in conformance with SONET/SDH, 10
Gigabit Ethernet (10GbE) and 10 Gigabit Fibre
Channel (10GFC) transmission standards. The
figure below shows a typical network
application. The other application block
diagrams are shown on page 2.
On-chip clock synthesis PLL components are
contained in the S19260 chip, allowing the use
of a slower external transmit clock reference.
The chip can be used with 155.52 MHz or 622.08
MHz (or equivalent FEC/10GbE/10GFC rates)
reference clocks, in support of existing system
clocking schemes. The low-jitter LVDS interface
guarantees compliance with the bit-error rate
requirements of the Telcordia and ITU-T
standards.
Overview
The S19260 transceiver incorporates SONET/
SDH/10 GbE/10GFC serialization functions. This
chip can be used to implement SONET/10 GbE/
10GFC equipment, which consists primarily of
the serial transmit interface. The chip includes
parallel-to-serial conversion and system timing.
TIA
System Block Diagram with the S19260
ORX
OTX
AMCC Suggested Interface Devices
The sequence of operations is as follows:
Transmitter Operations
Internal clocking and control functions are
transparent to the user.
RUBICON
(S19227)
GANGES III
(S19202CBI20)
HUDSON 2.0
(S19203)
KHATANGA
(S19205)
MEKONG
(S19204)
S19233
LD
• 16-bit parallel input
• Parallel-to-serial conversion
• Serial data output
• Serial clock output
10G Clk
data
P R O D U C T B R I E F
S19260
AMCC
OC-192/48/12/3 DW/FEC/PM and
ASYNC Mapper Device with Strong
FEC
STS-192 POS/ATM SONET/SDH
Mapper
Variable Rate Digital Wrapper
Framer/Deframer, Performance
Monitor, and FEC Device
STS-192c SONET/SDH Framer/Map-
per with Integrated MAC
STS-192 Pointer Processor
Dual CDR imbedded in XFP module
16
KHATANGA
MEKONG
RUBICON
GANGES
HUDSON
AMCC

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s19260 Summary of contents

Page 1

... STS-192 SONET/SDH/FEC/GbE/FC 16-bit Mux with 10G Clock Features Description • Operational from 9.9 Gbps to 11.32 Gbps The S19260 Mux chip is a fully integrated • On-chip High-Frequency PLLs for Clock serialization SONET STS-192/10 Gigabit Recovery and Clock Gen. Ethernet/Fiber Channel device with 10G clock • ...

Page 2

... Enable Adaptive ISI Mitigation Figure 1. Mid-Plane Application Block Diagram Enable Adaptive Post-Amplifier Offset Control Enable Adaptive ISI Mitigation Disable EDC / 10G Clock MDIO/I2C /SPI AMCC ASIC 16 OR S19260 XFP MODULE FRAMER 16 OR S19261 FEC Compensates up to 24" of FR-4 Figure 2. XFP Application Block Diagram 16 C ...

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