zl50012 Zarlink Semiconductor, zl50012 Datasheet
zl50012
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zl50012 Summary of contents
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... Copyright 2002-2006, Zarlink Semiconductor Inc. All Rights Reserved. Flexible 512-ch Digital Switch Ordering Information ZL50012/QCC 160 Pin LQFP ZL50012/GDC 144 Ball LBGA ZL50012QCG1 160 Ball LQFP* Trays, Bake & Drypack ZL50012GDG2 144 Ball LBGA** Trays, Bake & Drypack *Pb Free Matte Tin **Pb Free Tin/Silver/Copper -40°C to +85°C • ...
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... Mb/s or 8.192 Mb per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ 0-15) to support the use of external high impedance control buffers. The ZL50012 has features that are programmable on per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control. ...
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... Connection Memory Block Programming 2.6 Bit Error Rate (BER) Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7 Quadrant frame programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.0 JTAG Support 4.1 Test Access Port (TAP 4.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3 Test Data Register 4.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.0 Detail Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ZL50012 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50012 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure LQFP (JEDEC MS-026) Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 144 Ball LBGA Pinout Diagram Figure 4 - Input Timing when (CKIN2 to CKIN0 bits = 010) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 - Input Timing when (CKIN2 to CKIN0 bits = 001) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register ...
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... Table 27 - Stream Output Offset Register (SOOR8 to SOOR15 Table 28 - Address Map for Memory Locations (512 x 512 DX, MSB of address = 1 Table 29 - Connection Memory Bit Assignment when the CMM bit = Table 30 - Connection Memory Bits Assignment when the CMM bit = ZL50012 List of Tables 5 Zarlink Semiconductor Inc. ...
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... Input Jitter Tolerance with Frame Boundary Determinator“ 37 Table 15 -, “Control Register (CR) Bits“ - bits , “FBDMODE“ and , “FBDEN“ ZL50012 • Added a new section to describe the improved input jitter tolerance with the frame boundary determinator. • Renamed bit 15 from Unused to FBDMODE and added description to clarify the frame boundary determinator operation ...
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... VSS VDD 156 157 RESET 158 TDo 159 NC 160 NC Figure LQFP (JEDEC MS-026) Pinout Diagram ZL50012 160 Pin LQFP 0.5mm pin pitch JEDEC MS-026 (Top View) 10 Zarlink Semiconductor Inc. Data Sheet VDD ...
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... STo2 D STo3 E STo5 F STo6 G STOHZ 6 H STo9 J STo11 K STOHZ 9 L STOHZ 10 M STo14 Figure 144 Ball LBGA Pinout Diagram ZL50012 FPo2 FPo0 ICONN IC1 IC0 ICONN NC3 TM1 3 1 CKo1 FPo1 CKo0 IC3 IC2 CLK ...
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... B12 4 A12 5 B11 6 A11 7 B10 8 A10 ZL50012 Name V Power Supply for the device: +3 (GND) Ground. ss TMS Test Mode Select (3.3 V Tolerant Input with internal pull- up): JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven ...
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... ICONN2 - ZL50012 Name SG1 APLL Test Control (3.3 V Input with internal pull-down): For normal operation, this input MUST be low. TM1 APLL Test Pin 1: For normal operation, this input MUST be low. TM2 APLL Test Pin 2: For normal operation, this input MUST be low ...
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... D12 - D15 L8, M9, L9, L5 111 M5 114 K7 ZL50012 Name FPo2 ST-BUS Frame Pulse Output 2 (5V Tolerant High Speed Three-state Output): ST-BUS frame pulse output which stays low for the frame boundary. Its frequency is 8 KHz. The polarity of this signal can be changed using the Internal Mode Selection register ...
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... STi14 - 15 157 D11 158 C11 1, 2, 29 82, 119 - 122, 159, 160 ZL50012 Name R/W Read/Write (5 V Tolerant Input): This input controls the direction of the data microprocessor access. DS Data Strobe (5 V Tolerant Input): This active low input works in conjunction with CS to enable the microprocessor port read and write operations ...
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... Mb/s respectively. The frequency of CKi must be twice the highest data rate. For example, if users present the ZL50012 with 2.048 Mb/s and 8.192 Mb/s input data, the device should be programmed to accept the input clock of 16.384 MHz and the frame pulse which stays low for 61 ns. ...
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... FPi FPINP = 1 CKi (16.384MHz) CKINP = 0 CKi (16.384MHz) CKINP = 1 Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register ZL50012 Input Frame Boundary Input Frame Boundary Input Frame Boundary 17 Zarlink Semiconductor Inc. Data Sheet Input Frame Boundary Input Frame Boundary Input Frame Boundary ...
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... Improved Input Jitter Tolerance with Frame Boundary Determinator The ZL50012 has a Frame Boundary Determinator (FBD) allowing substantial increase of the CKi input clock jitter tolerance. The FBD circuit is enabled by setting the Control Register bits FBDEN and FBDMODE to HIGH. By default the FBD is disabled. Both the FBDEN and FBDMODE bits should be set HIGH during normal operation. The device can have input clock jitter tolerance (on CKi and FPi) when the FBD is fully enabled ...
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... CKFP0 0 1 Table 2 - FPo0 and CKo0 Output Programming CKFP1 0 1 Table 3 - FPo1 and CKo1 Output Programming CKFP2 0 1 Table 4 - FPo2 and CKo2 Output Programming ZL50012 FPo0 CKo0 Low Cycle 244 ns 4.096 MHz 122 ns 8.192 MHz FPo1 CKo1 61 ns 16.384 MHz 122 ns 8 ...
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... MHz) CKOP = 1 Figure 9 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 1 FPo1 FP1P = 0 FPo1 FP1P = 1 CKo1 (16.384 MHz) CK1P = 0 CKo1 (16.384 MHz) CK1P = 1 Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 0 ZL50012 20 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz) CK2P = 1 Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 0 FPo2 FP2P = 0 FPo2 FP2P = 1 CKo2 (16.384 MHz) CK2P = 0 CKo2 (16.384 MHz) CK2P = 1 Figure 13 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 1 ZL50012 21 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz) STo 0 7 (2.048 Mb/s) STo (4.096 Mb/s) Channel 0 STo (8.192 Mb/s) Output Frame Boundary Figure 14 - ST-BUS Output Timing for Various Output Data Rates ZL50012 Channel Channel Channel ...
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... By default, all input streams have zero bit delay such that Bit 7 is the first bit that appears after the input frame boundary, see Figure 16. The input delay is enabled by Bit the Stream Input Delay Registers (SIDR). The input bit delay can vary from bits. ZL50012 ...
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... Last Channel -1 SToX Channel Delay = 2 Note Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively Output Frame Boundary Figure 17 - Output Channel Delay Timing Diagram ZL50012 Ch0 Bit Delay = 1 Ch0 ...
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... Fractional Bit Adv (Default) Fractional Bit Advancement = 1/4 bit SToY Bit 1 Fractional Bit Adv. = 1/4 bit Note Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively Figure 19 - Fractional Output Bit Advancement Timing Diagram ZL50012 Ch0 ...
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... No Adv.) STOHZ Y (With Adv.) Note Output Frame Boundary Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively Figure 20 - Example: External High Impedance Control Timing ZL50012 HiZ Ch1 Ch2 Ch3 STOHZ Advancement (Programmable in 4 steps of 15 1/4 bit) 26 Zarlink Semiconductor Inc ...
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... Table 6 - Variable Range for Output Streams Input Channel Delay OFF Input Channel Delay ON Output Channel Delay OFF Output Channel Delay OFF frames - α + (n- frames + (n-m) ZL50012 Input Channel Possible Input channel delay (α) Number ( 127 Output Channel ...
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... Frame N-2 Data (β Serial Output Data Frame N-3 Data (β > 1) Figure 23 - Data Throughput Delay when input channel delay is disabled and output channel delay is enabled for Input Ch0 switch to Output Ch0 ZL50012 Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data Frame N+3 Data 2 Frames + 0 ...
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... Serial Output Data Frame N-3 Data (β Serial Output Data Frame N-4 Data (β > 1) Figure 24 - Data Throughput Delay when input and output channel delay are enabled for Input ZL50012 Frame N+1 Frame N+2 Frame N+3 Frame N+1 Data Frame N+2 Data Frame N+3 Data Input Channel Delay:(from 1 to max# of channels, programmed by the STIN#CD6-0 bit) ...
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... MBPS bit or the MBPE bit to low. If the MBPE bit is used to terminate the block programming before completion, users have to set the MBPS bit from high to low before enabling other device operation Table 8 - Connection Memory in Block Programming Mode ZL50012 Zarlink Semiconductor Inc ...
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... Bit Error Rate (BER) Test The ZL50012 has one on-chip BER transmitter and one BER receiver. The transmitter can transmit onto a single STo output stream only. The transmitter provides a BER sequence (2 from any channel in the frame and lasts from one channel up to one frame time (125 µs). The transmitter output ...
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... No bit replacement occurs in Quadrant 2 Table 12 - Quadrant Frame 2 LSB Replacement STIN#QEN3 1 Replace LSB of every channel in Quadrant 3 with "1" bit replacement occurs in Quadrant 3 Table 13 - Quadrant Frame 3 LSB Replacement ZL50012 Quadrant 1 Quadrant ...
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... Test Access Port (TAP) Controller. 4.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50012 test functions. It consists of three input pins and one output pin as follows: • Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on- chip clock and thus remains independent in the functional mode ...
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... Instruction Register The ZL50012 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four- bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO during data register scanning ...
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... H 114 H 115 H 116 H 117 H 118 H 119 H 11A H Table 14 - Address Map for Device Specific Registers ZL50012 CPU Register Access R/W Control Register, CR R/W Internal Mode Selection, IMS R/W BER Start Receive Register, BSRR R/W BER Length Register, BLR BER Count Register, BCR Reserved Reserved Reserved R/W ...
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... ZL50012 External CPU Address Access A11 - A0 11B R/W Stream13 Input Delay Register, SIDR13 H 11C R/W Stream14 Input Control Register, SICR14 H 11D R/W Stream14 Input Delay Register, SIDR14 H 11E R/W Stream15 Input Control Register, SICR15 H 11F R/W Stream15 Input Delay Register, SIDR15 H 200 R/W Stream0 Output Control Register, SOCR0 ...
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... CKFP0 Output ST Bus clock CKo0 and frame pulse FPo0 Selection. When this bit is low, CKo0 is 4.096 MHz clock and FPo0 is 244 ns wide frame pulse When this bit is high, CKo0 is 8.192 MHz clock and FPo0 is 122 ns wide frame pulse ZL50012 ...
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... Output Stand By Bit: This bit enables the STo0 - 15 and the STOHZ 0 -15 serial out- puts. The following table describes the HiZ control of the serial data outputs MS2-0 Memory Select Bit. These bits are used to select connection memory or data memory: Table 15 - Control Register (CR) Bits (continued) ZL50012 CKFP ...
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... MBPE bit in the control register is set to high and the MBPS bit is set to high, the con- tents of the bits BPD0 to BPD2 are loaded into Bit 0 to Bit 2 of the connection memory. Bit 3 to Bit 11 of the connection memory are zeroed. Table 16 - Internal Mode Selection (IMS) Register Bits ZL50012 ...
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... BER Receive Stream Address Bits: The binary value of these bits refers to the input stream which receives the BER data BRCA6 - 0 BER Receive Channel Address Bits: The binary value of these bits refers to the input channel in which the BER data starts to be compared. Table 17 - BER Start Receiving Register (BSRR) Bits ZL50012 CK2P ...
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... Bit Name BC15 - 0 BER Count Bits: The binary value of these bits refers to the bit error counts. When it reaches its maximum value of Hex FFFF, the value will not be changed any more Table 19 - BER Count Register (BCR) Bits ZL50012 ...
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... When this bit is high, the LSB of every channel in this quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7, Ch0 to 15 and Ch0 to 31 for 2.048 Mb/s, the 4.096 Mb/s and 8.192 Mb/s mode respectively. Table 20 - Stream Input Control Register (SICR0 to SICR7) ZL50012 , 106 , 108 ...
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... Bit Name Input Data Sampling Point Selection Bits STIN#SMP1 - STIN#DR2 - 0 Input Data Rate Selection Bits: Note: # denotes input stream from Table 20 - Stream Input Control Register (SICR0 to SICR7) (continued) ZL50012 , 106 , 108 , 10A , 10C , 10E , ...
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... When this bit is high, the LSB of every channel in this quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7, Ch0 to 15 and Ch0 to 31 for 2.048 Mb/s, the 4.096 Mb/s and 8.192 Mb/s mode respectively. Table 21 - Stream Input Control Register (SICR8 to SICR15) ZL50012 , 116 , 118 ...
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... Bit Name Input Data Sampling Point Selection Bits STIN#SMP1 - STIN#DR2 - 0 Input Data Rate Selection Bits: Note: # denotes input stream from Table 21 - Stream Input Control Register (SICR8 to SICR15) (continued) ZL50012 , 116 , 118 , 11A , 11C , 11E , ...
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... Input Stream# Bit Delay Bits: The binary value of these bits refers to the number of bits that the input stream will be delayed. This maximum value is 7. Zero means no delay. Note: # denotes input stream from Table 22 - Stream Input Delay Register (SIDR0 to SIDR7) ZL50012 , 107 , 109 ...
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... Input Stream# Bit Delay Bits: The binary value of these bits refers to the number of bits that the input stream will be delayed. This maximum value is 7. Zero means no delay. Note: # denotes input stream from Table 23 - Stream Input Delay Register (SIDR8 to SIDR15) ZL50012 , 117 , 119 ...
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... When this bit is high, the advancement unit is 1/4 bit. STOHZ Additional Advancement Bits STOHZ# STO#DR2 - 0 Output Data Rate Selection Bits: Note: # denotes input stream from Table 24 - Stream Output Control Register (SOCR0 to SOCR7) ZL50012 , 206 , 208 , 20A , 20C ...
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... STOHZ Advancement Control. When this bit is low, the advancement unit is 15.2 ns. When this bit is high, the advancement unit is 1/4 bit. STOHZ Additional Advancement Bits STOHZ# STO#DR2 - 0 Output Data Rate Selection Bits: Note: # denotes input stream from Table 25 - Stream Output Control Register (SOCR8 to SOCR15) ZL50012 , 216 , 218 , 21A , 21C , ...
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... The binary value of these bits refers to the number of bits that the output stream delayed. The maximum value is 7. Zero means no delay STO#FA1-0 Output Stream# Fractional Advancement Bits Note: # denotes input stream from Table 26 - Stream Output Offset Register (SOOR0 to SOOR7) ZL50012 , 207 , 209 , 20B ...
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... The binary value of these bits refers to the number of bits that the output stream delayed. The maximum value is 7. Zero means no delay STO#FA1-0 Output Stream# Fractional Advancement Bits Note: # denotes input stream from Table 27 - Stream Output Offset Register (SOOR8 to SOOR15) ZL50012 , 217 , 219 , 21B ...
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... Channels are used when serial stream is at 2.048 Mb/s. 3. Channels are used when serial stream is at 4.096 Mb/s. 4. Channels 0 to 127 are used when serial stream is at 8.192 Mb/s. Table 28 - Address Map for Memory Locations (512 x 512 DX, MSB of address = 1) ZL50012 A7 Stream # A6 A5 ...
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... Per-Channel Control Bits: These two bits control outputs. 0 CMM=1 Connection Memory Mode = 1. If this bit is set high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel message mode or per-channel BER mode. Table 30 - Connection Memory Bits Assignment when the CMM bit = 1 ZL50012 SSA0 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage ( ZL50012 Symbol I_3V V ...
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... CKi Input Clock Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD ZL50012 Sym. Level V 0.5V CT DD_IO V 0 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25° 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD Input Frame Boundary N FPi CKi Figure 26 - Frame Boundary Timing with Input Clock (cycle-to-cycle) Variation ZL50012 t FPIW t FPH t CKIP t CKIL Sym ...
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... V and are for design aid only: not guaranteed and not subject to production testing. DD Input Frame Boundary N FPi CKi Figure 27 - Frame Boundary Timing with Input Frame Pulse (cycle-to-cycle) Variation AC Electrical Characteristics - Input and Output Frame Boundary Alignment Characteristic 2 Input and Output Frame Offset ZL50012 Sym. Min. Typ FPV t FPV t FPV Sym ...
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... MHz) Input Frame Boundary t FBOS FPo2 CKo2 (32.768 MHz) FPo2 or FPo1 CKo2 or FPo1 (16.384 MHz) FPo1 or FPo0 CKo1 or CKo0 (8.192 MHz) FPo0 CKo0 (4.096 MHz) Figure 28 - Input and Output Frame Boundary Offset ZL50012 Output Frame Boundary 58 Zarlink Semiconductor Inc. Data Sheet ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD FPo0 CKo0 Output Frame Boundary Figure 29 - FPo0 and CKo0 Timing Diagram ZL50012 Sym. Min. t 220 FPW0 t 115 FODF0 t ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD FPo1 CKo1 Output Frame Boundary Figure 30 - FPo1 and CKo1 Timing Diagram ZL50012 Sym. Min FPW1 t 20 FODF1 t ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD FPo2 CKo2 Output Frame Boundary Figure 31 - FPo2 and CKo2 Timing Diagram ZL50012 Sym. Min FPW2 t 8 FODF2 t ...
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... FPi CKi (4.096 MHz) STi0 - 15 Bit0 Ch31 2.048 Mb/s STi0 - 15 Bit0 4.096 Mb/s Ch63 STi0 - 15 Bit1 Bit0 Ch127 Ch127 8.192 Mb/s Input Frame Boundary Figure 32 - ST-BUS Inputs (STi0 - 15) Timing Diagram ZL50012 ‡ Sym. Min. Typ. Max SIS2 3 t SIS4 3 t SIS8 3 t SIH2 3 ...
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... MHz) FPo0 CKo0 (4.096 MHz) STo0 - 15 Bit7 2.048 Mb/s Ch31 STo0 - 15 Bit7 4.096 Mb/s Ch63 STo0 - 15 Bit0 Ch127 8.192 Mb/s Output Frame Boundary Figure 33 - ST-BUS Outputs (STo0 - 15) Timing Diagram ZL50012 ‡ Sym. Min. Typ. Max SOD2 10 t SOD4 10 t SOD8 t SOD2 Bit7 ...
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... Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: High Impedance is measured by pulling to the appropriate rail with R CKo0-2 STo STo Figure 34 - Serial Output and External Control ZL50012 ‡ Sym. Min. Typ. t ...
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... Note 2: A delay of 600 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high CSD CS R/W A0-A11 D0-D15 READ D0-D15 WRITE DTA Figure 36 - Motorola Non-Multiplexed Bus Timing ZL50012 Sym. Min. Typ. Max CSS t 10 RWS t 5 ...
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... TDo Output Delay 9 TRST pulse width 10 Reset pulse width †Characteristics are over recommended operating conditions unless otherwise stated. TCK t TMSS TMS t TDIS TDi TDo TRST Figure 37 - JTAG Test Port Timing Diagram Reset ZL50012 Sym. Min. t 100 TCKP t 80 TCKH t 80 TCKL t 10 TMSS t ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...