zl50017 Zarlink Semiconductor, zl50017 Datasheet - Page 24

• Manufacturer Part Number: zl50017
• Description: 1 K Digital Switch
• Manufacturer: Zarlink Semiconductor

8.0
This feature allows for fast initialization of the connection memory after power up.
8.1
1. Set MBPE (bit 3) in the Control Register (CR) from low to high.
2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded
3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The val-
The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.
It takes at least two frame periods (250 µs) to complete a block program cycle.
MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.
MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.
Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low.
9.0
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 15 on page 39, Figure 16 on page 40, Figure 17 on page 41 and Figure 18 on page 42 for the
microprocessor timing.
Value
Bit
into CM_L.
ues stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3).
Memory Block Programming Procedure
Connection Memory Block Programming
Microprocessor Port
15
0
14
0
13
0
Table 2 - Connection Memory Low After Block Programming
12
0
11
0
10
0
Zarlink Semiconductor Inc.
9
0
ZL50017
8
0
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7
0
6
0
5
0
4
0
3
0
BPD2
2
BPD1
Data Sheet
1
BPD0
0