zl50050 Zarlink Semiconductor, zl50050 Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/7/727/zarlink_semiconductor_sml.jpg)
zl50050
Manufacturer Part Number
zl50050
Description
8 K-channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16, Or 32 Mbps , And 32 Inputs And 32 Outputs
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50050.pdf
(94 pages)
2.1.7.2
The output traffic on the Local streams are aligned based on the FP8o and C8o output timing signals. Operation of
stream data in Connection Mode or Message Mode is determined by the state of the LMM bit of the Local
Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection Memory.
The data source (i.e., from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local
Connection Memory. Refer to Section 9.1, Local Connection Memory, and Section 12.3, Local Connection Memory
Bit Definition for more details. Each output stream, LSTo0-15, can be individually set to operate at 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the LOBR1-0 bits in the Local Output Bit Rate Register
(LOBRR0-15). The Local streams can also be set to operate at 32.768 Mbps. When the MODE32L bit in the
Control Register is set high, the first 8 output streams, LSTo0-7, operate at 32.768 Mbps and the remaining 8
streams, LSTo8-15, will not be used and must be connected to a defined logic level.
2.1.8
The Backplane port has 16 input (BSTi0-15) and 16output (BSTo0-15) data streams.
The Backplane streams can be operated in one of two modes, Backplane Non-32 Mbps Mode and Backplane
32 Mbps Mode. The Backplane stream data rates are not affected by the operating mode of the Local port. The
operating mode of the Backplane side is determined by the state of the Control Register bit MODE32B. Setting this
bit HIGH will invoke the Backplane 32 Mbps Mode. Setting the bit LOW will invoke the Non-32 Mbps Mode. The
default value of this bit on device reset is LOW. The timing of the input and output clocks and frame pulses is shown
in Figure 7, Input and Output (Generated) Frame Pulse Alignment for Different Data Rates.
Backplane Non-32 Mbps Mode: Each of the Backplane streams (BSTi0-15 and BSTo0-15) can be independently
programmed for a data rate of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps.
Backplane 32 Mbps Mode: 8 of the Backplane input streams (BSTi0-7) and 8 of the Backplane output streams
(BSTo0-7) operate at a fixed rate of 32.768 Mbps. In this mode, the remaining input and output streams are unused.
2.1.8.1
The input traffic on the Backplane streams are aligned based on the FP8i and C8i input timing signals. Each input
stream, BSTi0-15, can be individually set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by
programming the BIBR1-0 bits in the Backplane Input Bit Rate Register (BIBRR0-15). The Backplane streams can
also be set to operate at 32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 8 input
streams, BSTi0-7, operate at 32.768 Mbps and the remaining 8 streams, BSTi8-15, will not be used and must be
connected to a defined logic level.
2.1.8.2
The output traffic on the Backplane streams are aligned based on the FP8o and C8o output timing signals.
Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the
Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane
Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC
bit of the Backplane Connection Memory. Refer to Section 9.2, Backplane Connection Memory and Section 12.4,
Backplane Connection Memory Bit Definition for more details. Each output stream, BSTo0-15, can be individually
set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the BOBR1-0 bits in the
Backplane Output Bit Rate Register (BOBRR0-15). The Backplane streams can also be set to operate at
32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 8 output streams, BSTo0-7,
operate at 32.768 Mbps and the remaining 8 streams, BSTo8-15, will not be used and must be connected to a
defined logic level.
Backplane Port Rate Selection
Local Output Port
Backplane Input Port
Backplane Output Port
Zarlink Semiconductor Inc.
ZL50050
22
Data Sheet