zl50060gag2 Zarlink Semiconductor, zl50060gag2 Datasheet

zl50060gag2

Manufacturer Part Number

zl50060gag2

Description

16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 64 Input And 64 Output Streams Pin Compatible With Mt90869

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL50060GAG2.pdf (99 pages)

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Features

•

16,384-channel x 16,384-channel non-blocking

unidirectional switching.The Backplane and Local

inputs and outputs can be combined to form a

non-blocking switching matrix with 64 input

streams and 64 output streams

8,192-channel x 8,192-channel non-blocking

Backplane input to Local output stream switch

8,192-channel x 8,192-channel non-blocking

Local input to Backplane output stream switch

8,192-channel x 8,192-channel non-blocking

Backplane input to Backplane output switch

8,192-channel x 8,192-channel non-blocking

Local input to Local output stream switch

Rate conversion on all data paths, Backplane-to-

Local, Local-to-Backplane, Backplane-to-

Backplane and Local-to-Local streams

Backplane port accepts 32 input and 32 output

ST-BUS streams with data rates of 2.048 Mbps,

4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any

combination, or a fixed allocation of 16 input and

16 output streams at 32.768 Mbps

Local port accepts 32 input and 32 output ST-

BUS streams with data rates of 2.048 Mbps,

BSTi0-31

BSTo0-31

BCST0-3

BORS

FP8i

C8i

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Backplane

Interface

Timing Unit

Input

PLL

Figure 1 - ZL50060/1 Functional Block Diagram

DD_PLL

Connection Memory

(8,192 locations)

DD_IO

Backplane

DS CS R/W

Zarlink Semiconductor Inc.

DD_CORE

Backplane Data Memories

Microprocessor Interface

Local Data Memories

and Internal Registers

Tolerance, Per Stream Rate Conversion (2, 4, 8,

(8,192 channels)

16, or 32 Mbps), and 64 Inputs and 64 Outputs

A14-0

16 K-Channel Digital Switch with High Jitter

SS (GND)

•

4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any

combination, or a fixed allocation of 16 input and

16 output streams at 32.768 Mbps

Exceptional input clock jitter tolerance (17 ns for

16 Mbps or lower data rates, 14 ns for 32 Mbps)

Per-stream channel and bit delay for Local and

Backplane input streams

Per-stream advancement for Local and Backplane

output streams

Constant 2-frame throughput delay for frame

integrity

Per-channel high impedance output control for

Local and Backplane streams

DTA

Connection Memory

(8,192 locations)

ZL50060GAC

ZL50060GAG2

ZL50061GAG

ZL50061GAG2

RESET

Local

D15-0

**Pb Free Tin/Silver/Copper

TMS

Ordering Information

ODE

TDi TDo TCK TRST

-40 C to +85 C

Test Port

Output

Timing

Unit

256 Ball PBGA

256 Ball PBGA**

272 Ball PBGA

272 Ball PBGA**

Interface

Local

FP8o

FP16o

C8o

C16o

LSTi0-31

LSTo0-31

LCST0-3

LORS

ZL50060/1

Data Sheet

Trays

February 2006

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