zl50211 Zarlink Semiconductor, zl50211 Datasheet - Page 7

• Manufacturer Part Number: zl50211
• Description: 256 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Rout1,Rout2,Rout3,
Rout4,Rout5,Rout6,
Sout1,Sout2,Sout3,
Sout4,Sout5,Sout6,
DTA1, DTA2, DTA3,
DTA4, DTA5, DTA6,
Rout7,Rout8,
Signal Name
Sout7,Sout8
DTA7, DTA8
MCLK
ODE
Fsel
R/W
C4i
F0i
DS
Signals
Signals
Signal
Signals
Signal
Signal
Signal
Signal
Signal
Signal
Signal
Type
User
User
User
User
User
User
User
User
User
User
AF9,W30,C29,D30
AG8,V28,C26,C30
N2,AK28,N1,AK6,
B7,W27,A7,AH8,
A5,V30,A6,AH7,
AJ7,AK27,M28,
BGA Ball #
Zarlink Semiconductor Inc.
M29
M27
K29
V29
B26
B25
A16
A15
ZL50211
7
Receive PCM Signal Outputs (Output). Port 2 TDM
data output streams. Each Rout pin outputs serial
TDM data streams at 2.048 Mb/s with 32 channels per
stream.
Send PCM Signal Outputs (Output). Port 1 TDM
data output streams. Each Sout pin outputs serial TDM
data streams at 2.048 Mb/s with 32 channels per
stream.
Data Strobe (Input). This active low input works in
conjunction with CS to enable the read and write
operations. This signal is connected to all processors.
Read/Write (Input). This input controls the direction of
the data bus lines (D7-D0) during a microprocessor
access. This signal is connected to all processors.
Data Transfer Acknowledgment (Open Drain
Output). These active low outputs indicate that a data
bus transfer is completed. A pull-up resistor (1 K
typical) is required at these outputs.
Output Drive Enable (Input). This input pin is
logically AND’d with the ODE bit-6 of the Main Control
Register. When both ODE bit and ODE input pin are
high, the Rout and Sout ST-BUS outputs are enabled.
When the ODE bit is low or the ODE input pin is low,
the Rout and Sout ST-BUS outputs are high
impedance. This signal is connected to all processors.
Frame Pulse (Input). This input accepts and
automatically identifies frame synchronization signals
formatted according to ST-BUS or GCI interface
specifications.This signal is connected to all
processors.
Serial Clock (Input). 4.096 MHz serial clock for
shifting data in/out on the serial streams (Rin, Sin,
Rout, Sout).This signal is connected to all processors.
Frequency select (Input). This input selects the Mas-
ter Clock frequency operation. When Fsel pin is low,
nominal 20 MHz Master Clock input must be applied.
When Fsel pin is high, nominal 10 MHz Master Clock
input must be applied.This signal is connected to all
processors.
Master Clock (Input). Nominal 10 MHz or 20 MHz
Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock
source.This signal is connected to all processors.
Signal Description
Data Sheet