am79c984a Advanced Micro Devices, am79c984a Datasheet - Page 16

• Manufacturer Part Number: am79c984a
• Description: Enhanced Integrated Multiport Repeater Eimr
• Manufacturer: Advanced Micro Devices

b. Alternative reconnection algorithm—A data packet
A partitioned port can also be reconnected by disabling
and re-enabling the port.
All TP ports use the same reconnection algorithm; ei-
ther they must all use the standard algorithm, or they
must all use the alternative reconnection algorithm.
However, the reconnection algorithm for the AUI port is
programmed independently from that of the TP ports.
Detailed Functions
Reset
The eIMR device enters the reset state when the reset
(RST) pin is driven LOW. After the initial application of
power, the RST pin must be held LOW for a minimum
of 150 s. If the RST pin is subsequently asserted while
AUI Port
The AUI Port is fully compatible with the IEEE 802.3,
Section 7 requirement for an AUI port. It has the signals
associated with an AUI port: DO, DI, and CI.
The AUI port has two modes of operation: normal and
reverse. When configured for normal operation, the
functionality is that of an AUI port on a MAC (CI is an
input). When configured for reverse operation, the func-
tionality is that of an AUI on a MAU (CI is an output).
The mode of the AUI port is set during the trailing (ris-
ing) edge of the reset pulse, by the state of the AMODE
pin. A LOW sets the AUI port to its normal mode (CI In-
put) and a HIGH sets the AUI port to its reversed (CI
Output) mode.
The eIMR device can be connected directly to a MAC
through the AUI port. This requires that the AUI port be
configured for reverse operation. Refer to the Systems
Applications section for more details.
16
Function
Active-LOW Outputs
Active-HIGH Outputs
SO Output
DAT, JAM
Transmitters (TP and AUI)
Receivers (TP and AUI)
AUI Partitioning/Reconnection Algorithm
TP Partitioning/Reconnection Algorithm
Link Test Functions for TP Ports
Automatic Receiver Polarity Reversal Function
longer than 512-bit times (nominal) is transmitted by
the partitioned port without a collision.
Table 1. eIMR States after Reset
P R E L I M I N A R Y
State after Reset
HIGH
LOW
HIGH
HIGH IMPEDANCE
IDLE
ENABLED
STANDARD ALGORITHM
STANDARD ALGORITHM
ENABLED, TP PORTS IN LINK FAIL
DISABLED IF SI PIN IS HIGH
ENABLED IF SI PIN IS LOW
Am79C984A
power is maintained to the eIMR device, a reset dura-
tion of only 4 s is required. This allows the eIMR de-
vice to reset its internal logic. During reset, the eIMR
registers are set to their default values. Also during re-
set, the eIMR device sets the output signals to their in-
active state; that is, all analog outputs are placed in
their idle state, no bidirectional signals are driven, all
active-HIGH signals are driven LOW and all active-
LOW signals are driven HIGH. In a multiple eIMR sys-
tem, the reset signal must be synchronized to CLK.
See Figure 10 in the Systems Applications section.
The eIMR device also monitors the state of the SELI
SI, and AMODE pins on the rising (trailing) edge of
RST to configure the operating mode of the device.
Table 1 summarizes the state of the eIMR chip following
reset.
TP Port Interface
Twisted Pair Transmitters
TXD is a differential twisted-pair driver. When properly
terminated, TXD will meet the electrical requirements
for 10BASE-T transmitters as specified in IEEE 802.3,
Section 14.3.1.2.
The TXD signal is filtered on the chip to reduce har-
monic content per IEEE 802.3, Section 14.3.2.1
(10BASE-T). Since filtering is performed in silicon, TXD
can connect directly to a standard transformer, thereby,
eliminating the need for external filtering modules.
Proper termination is shown in the Systems Applica-
tions section.
Twisted Pair Receivers
RXD is a differential twisted-pair receiver. When prop-
erly terminated, RXD will meet the electrical require-
ments for 10BASE-T receivers as specified in IEEE
802.3, Section 14.3.1.3. The receivers do not require
Pull Up/Pull Down
Terminated
Either
N/A
N/A
N/A
N/A
No
No
No
No
0-1
,