am79m535 Advanced Micro Devices, am79m535 Datasheet - Page 11

• Manufacturer Part Number: am79m535
• Description: Metering Subscriber Line Interface Circuit
• Manufacturer: Advanced Micro Devices

Notes:
1. Unless otherwise noted, test conditions are BAT = –48 V, V
2. Overload level is defined when THD = 1%.
3. Balance return signal is the signal generated at V
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. These tests are performed with a longitudinal impedance of 90
6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
7. When the SLIC is in the Anti-sat 2 operating region, this parameter is degraded. The exact degradation depends on system
8. “Midpoint” is defined as the connection point between two 300
9. Fundamental and harmonics from 256 kHz switch-regulator chopper are not included.
10. Total harmonic distortion with metering as specified with a metering signal of 2.2 Vrms at the two-wire output, and a transmit
11. Noise with metering is measured by applying a 2.2 Vrms metering signal (measured at the two-wire output) and measuring
12. Tested with 0
13. Assumes the following Z
14. Group delay can be considerably reduced by using a Z
R
impedance (Z
nent formulas.)
matches the impedance programmed by Z
12 kHz and 135
design. The Anti-sat 2 region occurs at high loop resistances when V
signal of +3 dBm or receive signal of –4 dBm. The transmit or receive signals are single-frequency inputs, and the distortion
is measured as the highest in-band harmonic at the two-wire or the four-wire output relative to the input signal.
the psophometric noise at the two-wire and four-wire outputs over a 200 ms time interval.
the group delay to less than 2 s. The effect of group delay on linecard performance may be compensated for by using the
QSLAC™ or DSLAC™ devices.
DC1
= R
DC2
Note:
* A logic Low on E0 disables the DET output into the open-collector state.
= 31.25 k , C
T
)= 306 k
State
source impedance. 2 M
0
1
2
3
4
5
6
7
for frequencies greater than 12 kHz. These tests are extremely sensitive to circuit board layout.
T
resistive, receive input summing impedance (Z
network:
C3 C2 C1
0
0
0
0
1
1
1
1
DC
= 0.1 F, R
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VTX
Open Circuit
Ringing
Active
On-hook TX (OHT)
Tip Open
Reserved
Active Polarity Reversal
OHT Polarity Reversal
is specified for system design purposes only.
T
d
.
= 51.1 k , no fuse resistors, two-wire AC output impedance, programming
Table 1. SLIC Decoding
Two-Wire Status
153 k
TX
SLIC Products
by V
T
RX
56 pF
network such as that shown in Note 13 above. The network reduces
. This specification assumes that the two-wire AC load impedance
CC
= +5 V, V
series resistors connected between A(TIP) and B(RING).
and metallic impedance of 300
153 k
BAT
EE
Ring trip
Ring trip
Loop detector
Loop detector
Loop detector
Loop detector
Loop detector
Loop detector
RX
= –5 V, R
– V
) = 300 k
E0 = 1*
RSN
E1 = 0
AX
DET Output
– V
L
= 600 , C
BX
resistive. (See Table 2 for compo-
is less than approximately 17 V.
Ring trip
Ring trip
Ground key
Ground key
Ground key
Ground key
E0 = 1*
E1 = 1
HP
—
—
for frequencies below
= 0.22 F,
11