am79d2251 Advanced Micro Devices, am79d2251 Datasheet - Page 27

• Manufacturer Part Number: am79d2251
• Description: Dual Intelligent Subscriber Line Audio-processing Circuit Islac
• Manufacturer: Advanced Micro Devices

PCM Interface
Master Clock
For 2.048 MHz ±100 PPM, 4.096 MHz ±100 PPM, or 8.192 MHz ±100 PPM operation:
Notes:
1.
2.
3.
4.
5.
6.
No.
No.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
DCLK may be stopped in the HIGH or LOW state indefinitely without loss of information. When CS
makes a transition to the High state, the last byte received will be interpreted by the Microprocessor
Interface logic.
The PCM clock (PCLK or MCLK) frequency must be an integer multiple of the frame sync (FS)
frequency with an accuracy of 100 PPM. This allowance includes any jitter that may occur between
the PCM signals (FS, PCLK) and MCLK. The actual PCLK rate is dependent on the number of channels
allocated within a frame. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be
used for standard U.S. transmission systems.
TSCA is delayed from FS by a typical value of N • t
slot register.
t
the load circuitry. The maximum load capacitance on TSCA is 150 pF and the minimum pull-up
resistance is 360 .
The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs
last.
The ISLAC device requires 2.0 s between SIO operations. If the MPI is being accessed while the
MCLK (or PCLK if combined with MCLK) input is not active, a Chip Select Off time of 20 s is required
when accessing coefficient RAM.
TSO
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DRH
MCY
MCR
MCF
MCH
PCY
PCH
PCL
PCF
PCR
FSS
FSH
TSD
TSO
DXD
DXH
DXZ
DRS
MCL
FST
is defined as the time at which the output driver turns off. The actual delay time is dependent on
PCM clock period
PCM clock HIGH pulse width
PCM clock LOW pulse width
Fall time of clock
Rise time of clock
FS setup time
FS hold time
Delay to TSCA valid
Delay to TSCA off
PCM data output delay
PCM data output hold time
PCM data output delay to high-Z
PCM data input setup time
PCM data input hold time
PCM or frame sync jitter time
Period: 2.048 MHz
Period: 4.096 MHz
Period: 8.192 MHz
Rise time of clock
Fall time of clock
MCLK HIGH pulse width
MCLK LOW pulse width
Parameter
Parameter
Am79D2251
PCY
488.23
244.11
122.05
Min.
0.122
Min
–97
48
48
, where N is the value stored in the time/clock
48
48
30
50
10
25
5
5
5
5
5
Typ
488.28
244.14
122.07
Typ
t
7.8125
PCY
Max
488.33
244.17
122.09
15
15
80
70
70
70
97
Max
15
15
–30
Unit
Unit
µs
ns
ns
Note
No
2
3
4
2
27