89hpes16t4g2 Integrated Device Technology, 89hpes16t4g2 Datasheet - Page 11

• Manufacturer Part Number: 89hpes16t4g2
• Description: 16-lane, 4-port Gen2 Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

System Clock Parameters
AC Timing Characteristics
IDT 89HPES16T4G2 Data Sheet
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Refclk
T
T
V
V
V
V
V
T
T
T
T
V
V
Duty Cycle
Rise/Fall Matching
Z
1.
C-RISE
C-FALL
STABLE
PERIOD-AVG
PERIOD-ABS
CC-JITTER
C-DC
IH
IL
CROSS
CROSS-DELTA
RB
MAX
MIN
Parameter
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
PCIe Transmit
UI
T
T
MAX-JITTER
T
T
TX-EYE
TX-EYE-MEDIAN-to-
TX-RISE
TX- IDLE-MIN
Parameter
FREQ
, T
TX-FALL
Input reference clock frequency range
Rising edge rate
Falling edge rate
Differential input high voltage
Differential input low voltage
Absolute single-ended crossing point
voltage
Variation of V
edges
Ring back voltage margin
Time before V
Average clock period accuracy
Absolute period, including spread-spec-
trum and jitter
Cycle to cycle jitter
Absolute maximum input voltage
Absolute minimum input voltage
Duty cycle
Single ended rising Refclk edge rate ver-
sus falling Refclk edge rate
Clock source output DC impedance
Unit Interval
Minimum Tx Eye Width
Maximum time between the jitter median and maxi-
mum deviation from the median
TX Rise/Fall Time: 20% - 80%
Minimum time in idle
Description
CROSS
RB
is allowed
Description
over all rising clock
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
Table 9 Input Clock Requirements
Condition
Single-ended
Single-ended
11 of 32
Differential
Differential
Differential
Differential
Differential
Differential
Min
399.88
0.125
0.75
20
1
Gen 1
Typ
400
9.847
Min
+150
+250
-100
-300
1
100
500
-0.3
0.6
0.6
40
40
Max
400.12
0.125
1
Typical
199.94
Min
0.75
0.15
20
20
1
Gen 2
Typ
200
1
10.203
Max
+1.15
+550
+140
+100
125
2800
-150
150
60
60
4
4
Max
200.06
1
March 27, 2008
1
Units
Unit
MHz
V/ns
V/ns
ppm
ps
UI
UI
UI
UI
mV
mV
mV
mV
mV
ps
ns
ps
%
%
Ω
V
V