89hpes12n3 Integrated Device Technology, 89hpes12n3 Datasheet - Page 11

• Manufacturer Part Number: 89hpes12n3
• Description: 12-lane, 3-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES12N3 Data Sheet
T
MAX JITTER
T
ENTER TIME
T
1.
RX-EYE-MEDIUM TO
RX-IDLE-DET-DIFF-
RX-SKEW
Parameter
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a
JTAG
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
1.
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
Signal
Max time between jitter median & max deviation
Unexpected Idle Enter Detect Threshold Integration Time
Lane to lane input skew
1
,
GPIO
GPIO[7:0]
1.
2.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
The values for this symbol were determined by calculation, not by testing.
they are asynchronous.
Signal
1
Thigh_16a,
Symbol
Tpw_16d
Tper_16a
Tlow_16a
Tdz_16c
Thld_16b
Tsu_16b
Tdo_16c
Description
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
2
Symbol
2
Tpw_13b
Table 10 GPIO AC Timing Characteristics
Table 11 JTAG AC Timing Characteristics
JTAG_TCK falling
JTAG_TCK rising
Reference
2
Edge
Reference
none
none
Edge
11 of 28
None
Min Max Unit
Min
50
50.0
10.0
25.0
2.4
1.0
—
—
Min
—
1
Max
25.0
20
20
—
—
—
—
ns
Typical
Reference
Diagram
Timing
Unit
ns
ns
ns
ns
ns
ns
ns
1
Max
Reference
See Figure 4.
0.3
Diagram
10
20
Timing
1
Units
July 18, 2006
ms
UI
ns