89hpes3t3 Integrated Device Technology, 89hpes3t3 Datasheet - Page 6

• Manufacturer Part Number: 89hpes3t3
• Description: 3-lane, 3-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

Pin Characteristics
IDT 89HPES3T3 Data Sheet
Note: Some input pads of the PES3T3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
PCI Express Inter-
face
SMBus
General Purpose I/O
System Pins
EJTAG / JTAG
Function
1.
Schmitt Trigger Input (STI)
APWRDISN
JTAG_TCK
PE0RN[0]
PE0RP[0]
PE0TN[0]
PE0TP[0]
PE2RN[0]
PE2RP[0]
PE2TN[0]
PE2TP[0]
PE3RN[0]
PE3RP[0]
PE3TN[0]
PE3TP[0]
PEREFCLKN
PEREFCLKP
MSMBCLK
MSMBDAT
GPIO[9,7,2:0]
CCLKDS
CCLKUS
PERSTN
RSTHALT
SWMODE[2:0]
WAKEN
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
Pin Name
.
Table 7 Pin Characteristics
Type
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
6 of 32
Buffer
LVPECL/
LVTTL
LVTTL
LVTTL
LVTTL
CML
CML
Serial Link
High Drive
Diff. Clock
Type
Input
Input
STI
I/O
STI
STI
STI
STI
STI
1
Resistor
Internal
open-drain
pull-down
pull-down
pull-down
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Refer toTable 8
Notes
March 31, 2008