m36p0r8070e0 STMicroelectronics, m36p0r8070e0 Datasheet - Page 14

• Manufacturer Part Number: m36p0r8070e0
• Description: 256 Mbit X16, Multiple Bank, Multilevel, Burst Flash Memory 128 Mbit Burst Psram, 1.8 V Supply, Multichip Package
• Manufacturer: STMicroelectronics

Functional description
Table 2.
1. X = Don’t Care.
2. The DPD
3. WAIT signal polarity is configured using the Set Configuration Register command. See the M58PR256J datasheet for
4. A18 and A19 are used to select the BCR (Bus Configuration Register), RCR (Refresh Configuration Register) or DIDR
5. If ECR15 is set to '0', the Flash memory device cannot enter the Deep Power-Down mode, even if DPD
6. L can be tied to V
7. Depends on G
8. ECR15 has to be set to ‘1’ for the Flash memory device to enter Deep Power-Down.
9. BCR and RCR only.
10. Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to
14/22
Bus Read
Bus Write
Address
Latch
Output
Disable
Standby
Reset
Deep Power-
Down
Read
Write
Read
Configuration
Register
Program
Configuration
Register
Standby
Deep Power-
Down
details.
(Device ID Register).
‘0’, and E has to be maintained High, V
Operation
(10)
F
(9)
signal polarity depends on the value of the ECR14 bit.
Main operating modes
F
.
V
V
memory can be enabled at a
V
V
V
V
E
Any Flash memory mode is
X
IH
IH
IH
IL
IL
IL
IL
F
Flash memories must be
allowed. Only one Flash
if the valid address has been previously latched.
V
V
V
G
X V
X
X
X
IH
IH
IL
F
W
V
V
V
X V
X
X V
IH
IH
IH
disabled
IL
F
time
RP
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IL
F
asserted
asserted
asserted
asserted
asserted
asserted
asserted
DPD
IH
de-
de-
de-
de-
de-
de-
, during Deep Power-Down mode.
(1)
F
(2)
(5)
(5)
(5)
(5)
(5)
(5)
(8)
Low-Z V
Low-Z V
Low-Z V
Low-Z V
WAIT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
(3)
V
V
V
IL
IL
X
X
X
X
X
X
L
IL
IL
IL
IL
IL
(6)
(6)
Only one Flash memory can be enabled at a
V
V
V
V
V
V
E
IH
IH
IL
IL
IL
IL
P
CR
Flash memories must be disabled.
V
V
V
V
V
X
IH
IH
IL
IL
IL
Any PSRAM mode is allowed.
P
PSRAM must be disabled.
V
V
G
X V
X V
X
X
IL
IL
P
W
V
V
X
X
IH
IH
IH
IL
P
LB
V
V
V
time.
X
X
X
IL
IL
IL
P
UB
V
V
V
X
X
X
IL
IL
IL
P
X1(DIDR)
00(RCR)
00(RCR)
10(BCR)
10(BCR)
A19
A18-
Valid
Valid
(4)
F
is asserted.
M36P0R8070E0
BCR/
A20-
RCR
A17
A22
data
A0-
X
or Hi-Z
BCR/RC
contents
data out
data out
PSRAM
data out
PSRAM
R/DIDR
data in
data in
DQ15-
Flash
Flash
Flash
DQ0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
(7)